Systems Engineer

• Apr 2019 - Present

Systems Engineer @ SHIELD HARDWARE

• Aug 2015 - Apr 2019

Architected and designed several projects for NVIDIA Shield, including Jetson Nano. Architected and designed several projects for NVIDIA Shield, including Jetson Nano.

Co-founder

• Jun 2013 - Aug 2015

We build semiconductors and micro-electrics in a whole new way, in short we bring back the "Garage"​ to the vocabulary of the semiconductor industry • We design Analog/Mixed Signal Integrated Circuits and Systems Products. • We believe that multidisciplinary talent and experience are what keep us sharp. • We fuel IC design innovation with new business models & social networking technology. Our unique approach depends on restoring the "Garage" concept back in semiconductor industry by maximizing the chance for great circuit and system IC designers to develop and prototype their ideas all the way to proven silicon. We provide all the key means to design, verify, exchange and monetize their design work. All online, and affordable! A dream come true. Show less

Owner & Manager

• May 2013 - Nov 2013

Design Engineering Manager

• Jun 2012 - May 2013

Performed design QA for Cypress Non-Volatile SRAM products. Drove the design team integration after the acquisition of Ramtron International. Lead all aspects of transitioning Ramtron design team to Cypress systems and processes, including all post acquisition evaluations, training, organization and role definition.

Principal Design Engineer

• Aug 2009 - Jun 2012

Lead cross-functional engineering teams to develop high performance synchronous SRAM products. Lead the development effort of 65nm platform and derivative memory products. Deliver key analog blocks and systems for on-chip power management. Lead the development effort of the first 28nm memory product during the feasibility and pre-launch phase. Owned, defined and improved corporate engineering processes for chip design. Participated and led corporate review boards to QA the development of several Cypress products. Show less

Sr. Staff Design Engineer

• Aug 2006 - Aug 2009

Technical lead for designing different analog blocks for Cypress 65nm products, including PLLs, power systems, references and high-speed I/O’s. Lead the architecture and design of on-chip power management systems for 65nm memory products. Use statistical design methods to improve product yield, manufacturability and robustness.

Staff Design Engineer

• Jan 2005 - Aug 2006

Design on-chip linear regulators, voltage references, DLL's and high-speed DDR programmable-impedance I/O structures on 90nm for synchronous SRAM products. Lead the development of high-speed I/O test setups and drive package modeling to solve chip and system level signal integrity issues.

Staff Product Engineer

• Jun 2001 - Jan 2005

Designed lab experiments to analyze and debug of high performance memory products using various equipment and ATEs. Designed experiments to evaluate and solve signal integrity and timing issues for DDR and Synchronous SRAM interfaces. Developed Built-In Self Test (BIST) and integrated flow in production test. Worked jointly with the fab to solve design and yield related yield problems.