Experience

PARADE TECHNOLOGY LTD.

• China
• Retail

• Senior Staff Design engineer

  • Dec 2010 - Present

  Analog citcuit design  HDMI Repeater - Design a Serdes 3.4Ghz jitter cleaning RX - Design CDR top with Dual-loop structure Analog citcuit design  HDMI Repeater - Design a Serdes 3.4Ghz jitter cleaning RX - Design CDR top with Dual-loop structure



IDT

• United States
• Building Materials
• 1 - 100 Employee

• Senior design engineer

  • Jul 2004 - Dec 2010

  1. DDR3 Register Buffer (World No.1 marketing share) - Design product generation 1 & 2 as key member; design DDR3 2.133G interface in the lowest 1.16v power supply; design the top architecture and validate the critical timing path - Design a fix delay independent with voltage and temperature variation with a US patent filed - Support customers FA and new feature implant quickly 2. Advanced Memory Buffer (Most powerful revenue engine in company) - Design DDR2 800M receiver in 1.15v supply with extreme low power - Design DLL module with a US patent filed - Design the on-chip low drop regulators for the whole chip 3. Display port Timing Controller (First tape out sample and production) - Design DDR2 800M transmitter with impedance calibration - Design the whole chip ESD protection structure which passes ESD HBM 6kv 4. Multi-point LVDS (Production) - Design a new whole chip ESD structure which can pass ESD HBM 8kv in the over-voltage signal bus application with a US patent issued 5. High speed IO library for communication chip application (First tape out success) - Design the LVTTL library - Design all IO IBIS models and timing models including LVDS, HSTL and LVTTL 6. Setup IBIS model evaluation flow Show less