Shady Elbassiouny

Principal Engineer - Product Engineering at Astera Labs
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Location
San Jose, California, United States, US
Languages
  • English -
  • French -
  • Arabic -

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Ahmed Elhamy Mostafa

I have known Shady when he was a wireless application engineer at Intel. We were colleagues in the same team that worked on link and system level simulations to develop and evaluate solutions for 5G wireless networks. Our team worked on small cell enhancement technologies, such as higher order modulation and small cell on-off switching. From my perspective as a colleague, Shady demonstrated the capability of coding, writing, and collaboration with other team members. Shady wrote C++ and MATLAB codes for both the link and system level simulators. He is also prepared the relevant 3GPP standard contribution documents, patent proposals, and conference papers including the outcomes of our research and performance evaluations. One of these publications was initiated by an idea of his to take our 3GPP evaluations of small cell on-off switching one further step to propose another algorithm that outperformed the previously proposed algorithms. I have also known Shady during our study for the M.Sc. at the American University in Cairo. He finished all the course work with a GPA of 4.00. I had the chance to work with Shady on two team projects for signal processing and numerical analysis courses, where Shady contributed a lot of ideas and hard work to achieve the full mark in both. He was also a teaching assistant for graduate courses, which are challenging courses in terms of content and graduate students’ expectations. He was a TA for an undergraduate lab, where supervision and teaching capabilities are necessary to help the undergraduate students. It is worth noting that Shady maintained his commitment to work for industry on both research and product levels after leaving Intel as he worked in IoT research lab of Orange (research deliverables were prioritized) and network virtualization in Avidbeam (product/proof of concept were required). Shady also has the capability of professional self-development while on full-time position. Shady finished the courses of his M.Sc. at the American University in Cairo and his M.Eng. at the University of British Columbia while working in full-time positions in Intel/AvidBeam and Microchip Technology Inc., respectively. This indicates his capability of learning new concepts while working. The courses he took also span across various areas such as communications, optics, machine learning, and integrated circuits. In Vancouver, BC, Canada, while pursuing his M.Eng. degree from UBC, Shady started working for Microchip Technology Inc. where he writes codes in Python to test and characterize ICs. Although I cannot closely assess Shady's performance in the current position, I noticed his flexibility with different programming languages such as Python (at Microchip Technology Inc.), MATLAB, and C++ (at Intel). Shady is cooperative, friendly, hardworking, and initiative taker. He has also demonstrated the capability to work in different companies and meet their research or product requirements.

Bradley Buss

I am proud to recommend Shady Elbassiouny for mixed-signal characterization work on complex semiconductor devices. Shady worked for me in the Data Center Solutions Product Engineering team at Microchip from Sept 2018 to Dec 2021. In his time at Microchip, Shady ramped up very quickly, taking a leadership role in the optimization and characterization of new 16nm IP, including PLLs, high-speed SERDES and DDR interfaces. Shady demonstrated creative problem-solving skills in driving for root cause for silicon performance issues and identifying fixes and improvements to ensure robust circuit performance across silicon process, voltage, and temperature. Shady demonstrated strong written and spoken communication skills by authoring high quality characterization reports and by sharing those reports with Tier 1 customers and internal teams. Shady has shown continuous professional growth and has demonstrated commitment to our business objectives by going above and beyond typical responsibilities expected of him. I would love to have him back on my team in the future, and in the meantime, I am proud to recommend him to anyone looking for a strong characterization lead. Bradley Buss Senior Manager Product Engineering Data Center Solutions Microchip Technology

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Credentials

  • V93000 ST7 Product Engineering
    Advantest
    May, 2023
    - Sep, 2024
  • Leading Teams certification
    Microchip Technology Inc.
    Nov, 2021
    - Sep, 2024
  • V93000 ST7 RDI Digital User Training
    Advantest
    Jul, 2021
    - Sep, 2024
  • Occupational First Aid - Level 1
    WorkSafeBC
    Feb, 2021
    - Sep, 2024

Experience

    • United States
    • Semiconductor Manufacturing
    • 100 - 200 Employee
    • Principal Engineer - Product Engineering
      • Dec 2021 - Present

      • Optimizing yield for AsteraLab's CXL memory pooling solution (Leo). • Performing Product and Package Qualification. • Bringing-up Yield Management System, • Developing ATE FW that reduced test time and improved coverage multiple folds. • Creating ATE Test plans, Qualification Plans, and Efuse allocation. • Working with OSATs and Foundrys for manufacturing quality products • Optimizing yield for AsteraLab's CXL memory pooling solution (Leo). • Performing Product and Package Qualification. • Bringing-up Yield Management System, • Developing ATE FW that reduced test time and improved coverage multiple folds. • Creating ATE Test plans, Qualification Plans, and Efuse allocation. • Working with OSATs and Foundrys for manufacturing quality products

    • United States
    • Semiconductor Manufacturing
    • 700 & Above Employee
    • Senior Product Engineer II
      • Oct 2021 - Dec 2021

    • Senior Product Engineer I
      • Mar 2019 - Oct 2021

      Quality gateway for the production of millions of Microchip's ICs distributed by analyzing hardware requirements, creating elaborate test plans and executing characterization across PVT to detect production defects and maximize product profitability. Highlight achievements: - Saved $10M+ in RMAs by providing hardware fixes to parts in production. - Achieved a reduction in yield loss from 20% to <0.5% by formulating production program limits. - Root caused, redesigned, and… Show more Quality gateway for the production of millions of Microchip's ICs distributed by analyzing hardware requirements, creating elaborate test plans and executing characterization across PVT to detect production defects and maximize product profitability. Highlight achievements: - Saved $10M+ in RMAs by providing hardware fixes to parts in production. - Achieved a reduction in yield loss from 20% to <0.5% by formulating production program limits. - Root caused, redesigned, and fixed a 30% false failing production BIST affecting foundational IP on multiple products amending coverage holes. Projects/Technologies: DDR5, DDR4, LVCMOS, LVDS, DCSU Products: - Smart Memory Controller (SMC 1000 8x25G) - SmartROC RAID-on-Chip Controllers - Switchtec™ Gen4 PCIe® Switches - Flashtec NVMe 3016

    • Product Engineer
      • Sep 2018 - Feb 2019

      • Collaborating with cross functional design, application, validation, firmware, and development teams to troubleshoot and resolve complex test problems and demonstrate product performance to customer. • Creating pre-silicon verification testbenches for various device IPs • Design SmarTest ATE loadboard for high volume production testing used to investigate product non conformance, product defect identification, DC characterization, and DFT regions characterization through SCAN, IC Test,… Show more • Collaborating with cross functional design, application, validation, firmware, and development teams to troubleshoot and resolve complex test problems and demonstrate product performance to customer. • Creating pre-silicon verification testbenches for various device IPs • Design SmarTest ATE loadboard for high volume production testing used to investigate product non conformance, product defect identification, DC characterization, and DFT regions characterization through SCAN, IC Test, PMBIST, and BSDL. • Creating test plans, defining test requirements, specifying/acquiring equipment (signal generators, spectrum analyzers, digital supplies, oscilloscopes ) and following testing methodologies to validate silicon under test against target specifications on bench test equipment. • Developing test bench equipment setup for characterization/validation boards including the Python environment setup associated with the DUT connectivity to execute required test plans and perform root cause analysis on device misbehaviors. • Creating detailed documentational reports with characterization findings and statistical data analysis of under test IP performance across PVT. • Mentoring interns on automated test bench setup for data collection and analysis.

    • Netherlands
    • IT Services and IT Consulting
    • 1 - 100 Employee
    • Senior NFV Solution Engineer
      • Jan 2015 - Feb 2016

      • Lead a team of two engineers to co-develop the world’s largest proof of concept of Network Functions Virtualization (NFV) for mobile operators in collaboration with Intel and Etisalat Egypt • Prototyped a virtualized network environment using Openstack over a Linux system • Created a video optimization virtualized network function as part of the proof of concept using C under Linux • Lead a team of two engineers to co-develop the world’s largest proof of concept of Network Functions Virtualization (NFV) for mobile operators in collaboration with Intel and Etisalat Egypt • Prototyped a virtualized network environment using Openstack over a Linux system • Created a video optimization virtualized network function as part of the proof of concept using C under Linux

    • Egypt
    • Higher Education
    • 200 - 300 Employee
    • Research Assistant
      • Sep 2013 - Feb 2016

      Improved Decoder Likelihoods for 3G Cellular Uplink over Asynchronous Multi-Path Fading Channels

    • Teaching Assistant
      • Sep 2013 - May 2015

      • Teaching & preparing for "Digital Communications Lab" (Undergrad Course) • Teaching & preparing for "Stochastic Processes – Advanced Digital Communications" (Grad Course)

    • Germany
    • International Trade and Development
    • 1 - 100 Employee
    • Research And Development Engineer- IOT
      • Sep 2014 - Dec 2014

      • Published a conference paper on a new routing technique in wireless sensor networks • Developed a Wireless Sensor Network Matlab simulator from scratch • Published a conference paper on a new routing technique in wireless sensor networks • Developed a Wireless Sensor Network Matlab simulator from scratch

    • United States
    • Semiconductor Manufacturing
    • 700 & Above Employee
    • 5G Wireless Researcher
      • Jul 2012 - Apr 2014

      • Developing LTE/WiFi QoS aware offloading based on LTE Protocol Stack and written in C. • Modifying Intel propriety Matlab Simulator to study interference Mitigation techniques in heterogeneous Multi-RAT Networks, studying LTE Standards & New topics in LTE Rel-12 (LTE-Hi). • Published 2 Conference papers discussing small cells improvements in LTE • Developing LTE/WiFi QoS aware offloading based on LTE Protocol Stack and written in C. • Modifying Intel propriety Matlab Simulator to study interference Mitigation techniques in heterogeneous Multi-RAT Networks, studying LTE Standards & New topics in LTE Rel-12 (LTE-Hi). • Published 2 Conference papers discussing small cells improvements in LTE

    • Research Engineer
      • Feb 2012 - Jul 2012

      Worked on a project powered by Vodafone and NTRA regarding a study in the 3G network optimization, played an RA role studying a simulator in the 3G network (ATOLL), helped in developing an enhanced Scrambling code Clashes detection in 3G networks Using ATOLL Signal Level Analysis Capability. Worked on a project powered by Vodafone and NTRA regarding a study in the 3G network optimization, played an RA role studying a simulator in the 3G network (ATOLL), helped in developing an enhanced Scrambling code Clashes detection in 3G networks Using ATOLL Signal Level Analysis Capability.

    • Intern
      • Aug 2011 - Oct 2011

      Advanced Network courses (BGP- MPLS – OSPF)/GPRS Advanced Network courses (BGP- MPLS – OSPF)/GPRS

    • France
    • Motor Vehicle Parts Manufacturing
    • 700 & Above Employee
    • Intern - Tooling Engineer
      • Sep 2011 - Sep 2011

      Developing a Matlab Tool that processes excel sheets (GUI/HTML reporting) Developing a Matlab Tool that processes excel sheets (GUI/HTML reporting)

    • Trainee
      • Jul 2011 - Aug 2011

      Modifying an LTE Simulator to introduce the effect of Pico Cells in LTE Performance (OOP Matlab) Modifying an LTE Simulator to introduce the effect of Pico Cells in LTE Performance (OOP Matlab)

    • Intern
      • Apr 2011 - May 2011

      CCNA Internship course during college period CCNA Internship course during college period

    • Trainee
      • Aug 2010 - Oct 2010

      Studied GSM, CDMA (basics), Frequency planning, base stations checkup, Handover optimization Studied GSM, CDMA (basics), Frequency planning, base stations checkup, Handover optimization

    • Egypt
    • IT Services and IT Consulting
    • 700 & Above Employee
    • Intern
      • Jul 2010 - Aug 2010

      Training at Giza Systems ( working on routers and switches and learning CCNA) Training at Giza Systems ( working on routers and switches and learning CCNA)

Education

  • The University of British Columbia
    Master of Engineering - MEng, Electrical, Electronics and Communications Engineering
    2016 - 2019
  • The American University in Cairo
    MSc. Electronics engineering, 4/4
    2013 - 2015
  • Cairo University
    Bachelor's degree, Engineering
    2007 - 2012
  • Manara Language School
    IGCSE, 121.3%
    2005 - 2007

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