Experience

MIATech LLC

• IT Services and IT Consulting
• 1 - 100 Employee

• FPGA Design Engineer

  • Nov 2015 - Present

  Development of video system for receiving, transmitting and processing video information.Used video interfaces - HDMI, FPDLink, DisplayPort, OpenLDI, GMSL3.Tools used: Xilinx Vivado, Mentor Graphics QuestaSim.FPGA used: Xilinx Kintex-7. Development of video system for receiving, transmitting and processing video information.Used video interfaces - HDMI, FPDLink, DisplayPort, OpenLDI, GMSL3.Tools used: Xilinx Vivado, Mentor Graphics QuestaSim.FPGA used: Xilinx Kintex-7.



Scientific Research Institute of Communication and Control Systems JSC

• Development Team Lead

  • Apr 2014 - Sep 2015

  Development of software-defined radio platform (SDR platform).Creating the concept of a hardware and software system, developing circuit diagrams, developing FPGA firmware, organizing and monitoring the work of a DSP programmer, a programmer of embedded MCU software, a mathematician programmer of algorithms for sound and data processing, a PC programmer.SDR module FPGA design (FPGA Kintex-7; DSP TMS320; 500MSPS JESD204B ADC; 2GSPS JESD204B DAC).IP cores used: Xilinx JESD204B, SRIO, MIG, DDS, FIR, CIC, etc.Tools used: Mathworks Matlab, Xilinx Vivado.FPGA used: Xilinx Kintex-7.



Lutch JSC - a part of JSC Vega Radio Engineering Corporation

• FPGA Design Engineer

  • Mar 2013 - Mar 2014

  Development of a video system that receives compressed video information, it's decoding according to the JPEG2000 standard, conversion of parameters and characteristics of video information and it's transmission over the FiberChannel.Tools used: Xilinx ISE, Synplicity Pro, Identify Debugger.FPGA used: Xilinx Virtex-6. Development of a video system that receives compressed video information, it's decoding according to the JPEG2000 standard, conversion of parameters and characteristics of video information and it's transmission over the FiberChannel.Tools used: Xilinx ISE, Synplicity Pro, Identify Debugger.FPGA used: Xilinx Virtex-6.



"Garant-Plus" LLC

• FPGA Design Engineer

  • Apr 2009 - Feb 2013

  Development of a system for capturing and analyzing Ethernet traffic (100M-1G).Development of a system for hardware noise reduction of voice channels.As part of the work on the projects, cooperation with OdinTelesystems Inc., Texas, USA was carried out.Tools used: Xilinx ISE, Synplicity Pro, Identify Debugger. Lattice ispLEVER.FPGA used: Xilinx Virtex-5, Virtex-6. LatticeXP2. Development of a system for capturing and analyzing Ethernet traffic (100M-1G).Development of a system for hardware noise reduction of voice channels.As part of the work on the projects, cooperation with OdinTelesystems Inc., Texas, USA was carried out.Tools used: Xilinx ISE, Synplicity Pro, Identify Debugger. Lattice ispLEVER.FPGA used: Xilinx Virtex-5, Virtex-6. LatticeXP2.



Science Technical Center "Kami-Sever" LLC

• Head of section FPGA Design

  • Feb 2008 - Feb 2009

  Leading the development team, developing and defining the concept and structure of the systems and modules, developing the FPGA firmware (modeling, verification, logic synthesis, place and route, timing analysis), developing an electrical circuit of the devices, testing and debugging prototypes.Development of a system for capturing and analyzing STM (synchronous digital hierarchy) of traffic and auxiliary information (STM - 1/4/16 levels).Tools used: Xilinx ISE, Synplicity Pro, Identify Debugger.FPGA used: Xilinx Virtex-5.

• Senior FPGA Design Engineer

  • Sep 2007 - Feb 2008

  Development of an integrated system for capturing and analyzing voice traffic and auxiliary information on E1 lines (256 E1 analysis channels).Tools used: Xilinx ISE, Synplicity Pro, Identify Debugger.FPGA used: Xilinx Virtex-4.

• FPGA Design Engineer

  • Mar 2005 - Sep 2007

  Development of a system for capturing and analyzing voice traffic on E1 lines (4 channels of E1 analysis). Tools used: Xilinx ISE, Synplicity Pro, Identify Debugger.FPGA used: Xilinx Spartan-3.