Satbir Kahlon
MTS at Intermolecular- Claim this Profile
Click to upgrade to our gold package
for the full feature experience.
Topline Score
Bio
Experience
-
Intermolecular
-
United States
-
Nanotechnology Research
-
1 - 100 Employee
-
MTS
-
Mar 2011 - Present
Supporting Development of a Selector for NVM Based On Chalcogenide Materials - Exploring chalcogenide material spaces in multiple phases and optimizing the processes to achieve desired selector behavior for NVM using PVD system. - Strategizing material availability and exploration in multiple phase, system availability, analysis requirements to provide desired deliverable to customer. - Managing process integration, safety protocols a contamination mitigation due to toxicity nature of the material. Combinatorial HPC Wet Etch Process Development - Screened multiple chemistries and developed new residual removal and anisotropic etch formulations using combinatorial HPC system. Demonstrated the processes on the customer products that led to a successful royalty business. Installed and Supported customer install. - Led combinatorial HPC dispense system’s re-design to eliminate the cross contamination and improve the reliability/functionality. Introduced new design to improve robustness of wet etch tool and reduce defects. Cost Saving on Wafer Usages - Implemented wafer reclaim program and qualified new vendors for the comparative edge to negotiated price of new prime wafers and saved over $300k/year ($1million run rate). Show less
-
-
-
WaferTech
-
United States
-
Semiconductor Manufacturing
-
300 - 400 Employee
-
Sr. Thin Film Process Engineer
-
Mar 2010 - Mar 2011
Sustained/optimized HDP STI, PECVD ILD & IMD Thin Film dielectric processes - Improved 0.15um & 0.18um STI gap fil and within wafer non-uniformity to minimize poly-line bridging for higher yield, enhanced from 90% to > 95%. - Optimized HDP STI chamber clean process to eliminate 1st wafer thickness and particle effect to enhance yield. - Monitored RTM and SPC Automotive Grade products and maintained Cp/Cpk >1.67 to achieve yield >95%. Implemented APC to fine-tune process timing in-between the wet cleans. - Investigated process timing and sequencing and improved system throughput by 7.4% (WPH). Consolidated process monitors to improve system availability. - Reviewed daily SPC and RTM for OOC/OOS to determine process repeatability and failures and dispositioned impacted lots based on release WAT/Cp criteria. Generated 8D failure analysis reports to determine root causes & FMEA risk assessment report. Show less
-
-
-
Novellus Systems acquired by Lam Research Corporation
-
Semiconductor Manufacturing
-
400 - 500 Employee
-
Process development Engineer
-
Sep 2004 - Dec 2009
HDP gap fil capability using SPEED (Simultaneous Profile Evolution by Etch and Dep) - Developed HDP SPM-F processes with emphasis on higher AR, void free, no clipping gap fill using CVD deposition/sputter and etch (NF3 and/or H2) for STI and ILD applications. - Optimized plasma clean process using OES-EPD and IR-EPD to obtain a real end point that resulted in higher throughput and reduced defectivity. - Investigated the effect of Magnetic Shielding on the gap fil asymmetry and hat etch profile and also modulated the plasma incident away from the chamber components to reduce Al metal contamination in the film. Led CIP Team to Enhance SPEED System Performance - Performed failure analysis to determine the root cause, participated in re-design and re-testing and retrofitted new process/hardware at both Novellus and customer sites. - Characterized high/low frequency RF powers for high impedance caused due to chamber conditions: pressure, gases, flows, etc and re-designed underperforming RF components to improve the system reliability and the fire hazards. - Resolved particle/thickness issue (orifice clogging) caused due to processing timing/sequencing on customer site and achieved OUT STANDING AWARD for being out of the box thinking. - Optimized CESC (Columbic Electrostatic Chuck) design to obtain uniform temperature distribution across the wafer for IMD and PSVN layers. Successful Process Start Ups (HDP SPEED, PECVD, PNL-WCVD and Cu electroplating) - Started process and supported pre- & post-sale activities to gain highest strategic position and customer satisfaction. - Optimized STI SPM-F process to extend STI gap fill from 90nm to 65nm with AR 7:1. Show less
-
-
-
Torrex Equipment Corporation
-
United States
-
Appliances, Electrical, and Electronics Manufacturing
-
Sr. Process Engineer
-
Aug 2000 - Jun 2004
LPCVD Doped/Undoped Amorphous/Polysilicon and Low/High Temperature LPCVD/ALD SiN - Supported the design team to develop a system from an alpha-phase to a final product. - Developed/demonstrated phosphine/Arsine doped Amorphous/Polysilicon that results in 1st tool sale. - Developed low temperature silicon nitride (LTSiN) process with equivalent properties to thermal Si3N4. LPCVD Doped/Undoped Amorphous/Polysilicon and Low/High Temperature LPCVD/ALD SiN - Supported the design team to develop a system from an alpha-phase to a final product. - Developed/demonstrated phosphine/Arsine doped Amorphous/Polysilicon that results in 1st tool sale. - Developed low temperature silicon nitride (LTSiN) process with equivalent properties to thermal Si3N4.
-
-
-
Quester Technology Inc
-
United States
-
Semiconductors
-
Sr. Process Engineer
-
Apr 1997 - Feb 2000
APCVD Doped/Undoped Dielectric Process for STI, ILD, IMD and Spacers - Developed and demonstrated NSG, PSG, BPSG processes to achieve good gap fil, higher aspect ratios and reduced silicon and silicon nitride selectivity. - Supported CIP to reduce build up on dispersion heads and optimize in-situ cleaning to improve system throughput. - Started up tool in the field and supported the post-sale activities to achieve highest customer satisfaction. APCVD Doped/Undoped Dielectric Process for STI, ILD, IMD and Spacers - Developed and demonstrated NSG, PSG, BPSG processes to achieve good gap fil, higher aspect ratios and reduced silicon and silicon nitride selectivity. - Supported CIP to reduce build up on dispersion heads and optimize in-situ cleaning to improve system throughput. - Started up tool in the field and supported the post-sale activities to achieve highest customer satisfaction.
-
-
Education
-
San Jose State University
MSE, Electronic Materials and Devices