Experience

Astera Labs

• United States
• Semiconductor Manufacturing
• 100 - 200 Employee

• Sr. Product Manager

  • May 2022 - Present

  Vancouver, British Columbia, Canada



Microchip Technology Inc.

• United States
• Semiconductor Manufacturing
• 700 & Above Employee

• Product Manager, CXL Products

  • Oct 2021 - May 2022

  Burnaby, British Columbia, Canada • Developing roadmap for Microchip’s new and exciting product offerings for server, storage, cloud, and data center segment • Execution of product development strategies through strong collaboration with engineering teams for feature development, schedule management, development of security processes, customer communication plans and updates to product line • Establishing strong partnerships with customers to drive next generation products

• Manager, Applications Eng

  • May 2020 - Feb 2022

  Burnaby, British Columbia, Canada a) Managing upwards of $100 million Tier-1 Data center, High Performance Computing and Hyper scale customer accounts supporting RAID controllers, SAS Expanders, PCIe Switches. Includes leading architectural discussions with customers, leading roadmap feature discussions with marketing/sales teams, issue debugging on multi-threaded products with MIPS processors, creating customer documentation and providing technical training b) Member of Security Council for Data Center Solution… Show more a) Managing upwards of $100 million Tier-1 Data center, High Performance Computing and Hyper scale customer accounts supporting RAID controllers, SAS Expanders, PCIe Switches. Includes leading architectural discussions with customers, leading roadmap feature discussions with marketing/sales teams, issue debugging on multi-threaded products with MIPS processors, creating customer documentation and providing technical training b) Member of Security Council for Data Center Solution products. Duties include contributing towards security feature roadmap, security practices based on standards, security training content for internal and external customers utilizing expertise in Microsoft DICE/RiOT implementation c) Managing a team Firmware Applications Engineers supporting Tier-1 customers and leading programs for various Gen 4 SAS (24Gbps) and Gen 3/4 PCIe (32Gbps) products. Duties include- leading technical debugging, escalation management, managing cross functional teams to drive timely issue closure d) Expertise in high speed interfaces such as SAS, SATA, PCIe on protocol level. Experienced in use of high speed Oscilloscopes, logic/spectrum analyzers, protocol analyzers for debugging high speed interfaces.

• Technical Staff, Applications Engineering

  • Aug 2017 - Jul 2020

  Burnaby



PMC-Sierra is now Microsemi

• Semiconductor Manufacturing
• 300 - 400 Employee

• Staff Application Engineer

  • Feb 2014 - Jul 2017

  Vancouver, Canada Area FW/HW applications development and support for Tier 1 customers using PMC's Raid On chip Controllers (ROC) .



Seagate Technology

• United States
• Computer Hardware Manufacturing
• 700 & Above Employee

• Staff Engineer

  • Jul 2011 - Feb 2014

  AMK,Singapore EAO, Advanced Development Engineering High speed board design (schematic capture and layout rules), SPICE simulations, Hyperlynx simulations for signal integrity analysis / tests including Eye diagrams, measuring -Cross talk, reflections, EMI, TDR tests. Development of software/firmware applications for ddr3 with gcc-c++ on Fedora OS. FPGA prototyping: Designs based on integrating customized blocks (Verilog/VHDL) with different Altera hard and soft IP cores, Embedded… Show more EAO, Advanced Development Engineering High speed board design (schematic capture and layout rules), SPICE simulations, Hyperlynx simulations for signal integrity analysis / tests including Eye diagrams, measuring -Cross talk, reflections, EMI, TDR tests. Development of software/firmware applications for ddr3 with gcc-c++ on Fedora OS. FPGA prototyping: Designs based on integrating customized blocks (Verilog/VHDL) with different Altera hard and soft IP cores, Embedded firmware development (C++). Use of SignalTap analyzer for debugging. Test bench creation and ModelSim simulations. Static Timing Analysis. Validation and development of functional & data integrity tests, characterization of PHY on SATA, SAS, DDR3, USB 3 interfaces on SoCs in disk drives. Expertise in using high speed Oscilloscopes, logic analyzers, bus/protocol analyzers, Arbitrary waveform and signal generators. Customer support, failure analysis, interaction/support of FAE and sales/marketing teams. Show less



ESA Electronics (R&D)

• Firmware/Hardware development Engineer

  • Jun 2010 - Jul 2011

  Design and development of firmware and hardware for semiconductor burn-in test platform. VHDL/Verilog Coding including Floorplanning, Place & route on Xilinx Spartan platforms. Design, verification and debugging of large & complex design, over 10 layer PCBs with FPGAs, mixed signal SOCs including DDR2/3, PCIe, USB, Ethernet PHY and ADCs. Embedded FW development for FPGA using EDK and Altium Designer environment (C/C++).



ST-Ericsson

• Switzerland
• Semiconductor Manufacturing
• 500 - 600 Employee

• Hardware Application Engineer

  • Sep 2009 - Jun 2010

  Silicon Validation, hardware designing and characterization of USB analog transceivers.



Texas Instruments

• United States
• Semiconductor Manufacturing
• 700 & Above Employee

• Interface Applications Engineer

  • Jan 2006 - Aug 2009

  Hardware designing using Cadence tools, silicon validation and failure analysis using high speed scopes, Firmware debugging support, bus analyzers, logic analyzers for Texas Instruments USB, PCIe and other interface products. Provided world wide customer design support for designing with TI's high speed interface solutions through detailed schematic reviews, failure analysis and debugging customer designs (Firmware and Hardware). Supported regional sales engineers, marketing teams and… Show more Hardware designing using Cadence tools, silicon validation and failure analysis using high speed scopes, Firmware debugging support, bus analyzers, logic analyzers for Texas Instruments USB, PCIe and other interface products. Provided world wide customer design support for designing with TI's high speed interface solutions through detailed schematic reviews, failure analysis and debugging customer designs (Firmware and Hardware). Supported regional sales engineers, marketing teams and field application engineers. Extensive knowledge of USB 2.0/OTG complaince tests. Have been responsible for certification of TI's OTG products. Proficient knowledge of USB 2.0/OTG, PCIe, UART and 1394 protocols and specifications. Co authored application notes on XIO2000A HyperLynx7.7 PCIe Modeling and XIO2000A FAQ’s (available on TI’s website). Show less



University of Texas at Tyler

• United States
• Higher Education
• 700 & Above Employee

• Research Assistant

  • May 2004 - Dec 2005

  Successfully completed multiple research projects based on signal and image processing sponsored by Texas Instruments and US Naval post graduate school. Co-authored research papers which were presented in reputed conferences. Teaching assistant for under graduate electronics lab I/II.