Experience

GXC

• United States
• Wireless Services
• 1 - 100 Employee

• Senior RF Engineer

  • May 2018 - Present

  Indoor small cell backhaul echo channel and RF Self Interference Canceller (SIC) filter topology optimization and technology feasibility analysis. RF SIC filter network link optimization, hardware design and OTA demonstration of outdoor macro cell with RF/Digital SIC capability. Lead engineer for PCB design of Xilinx RFSoC FPGA SIC integrated with eNB and UE Backhaul small cell. Patent author of optimization process for SIC devices utilizing deployment scenario echo measurements and oscillator phase noise profiles. System/electrical/RF design, integration, and characterization of RF-photonic link hardware for optical neural network. Laser carrier and photonics chip interface module design for package-integrated laser, photonic ic, photodetector transceiver. Analysis of MIMO antenna network self-interference (SI) channels in deployed environment scenarios to determine optimized SIC topologies and performance expectations. Assessed feasibility of neural networks trained with SI channel datasets for use in SIC control functions. Hardware design for LTE/5G CBRS band mesh node relay product including M.2 module carrier PCB for CPE backhaul. Analysis of time-varying SI channel characteristics and extrapolation of dynamic system control requirements. Mentoring junior engineers. Project cost/resource estimation and tracking. Technical progress/status reporting. Show less



SPEC (Systems & Processes Engineering Corp)

• United States
• Defense and Space Manufacturing
• 1 - 100 Employee

• Principal RF Engineer

  • Oct 2013 - May 2018

  Responsible for design, integration, and characterization of RF front ends used in ADEP 1300, T4000, Blade, and Ultra DRFM product lines. Transceiver bands of operation include VHF, UHF, L, S, C, X, Ku and Ka. Form factors implemented include 3U VPX (VITA 46), proprietary circuit card buses, and connectorized configurations deployed in harsh environments and designed for manufacture. RF system synthesis, simulation, and optimization for multiple transceiver architectures was performed: frequency planning and spurious analysis of multi-IF, multi-octave tunable, broadband systems; noise figure; link budgets; and distortion. Transceiver interface, operation, and AGC achieved using on-board micro-controllers. Implemented sub-systems and sub-circuits include: wideband phase-locked synthesizers, low noise amplifiers, power amplifiers, bias controllers, image-rejection mixers/modulators/demodulators, SDLVA’s, peak detectors, switched filter banks, variable gain amplifiers and attenuators, tunable filters, etc. Experience acquired designing, documenting, integrating, and testing complex RF systems incorporating high speed data-converters, FPGA's, advanced DSP algorithms, and synchronous control techniques applied to radar and communication signals. Technical contributions made to successful research and business proposals. Experience gained supporting customer product integration and education. Simulation and design software used includes Genesys Spectrasys, Momentum, Orcad, Allegro, and filter synthesis tools. Proficiency achieved automating test equipment: network analyzers, vector signal generators, spectrum analyzers, high-speed oscilloscopes, power meters, etc. Programming languages used include Python, Matlab, C, and C#. Show less



Computer Science Lab 12, Kobe University, Japan

• Kobe, Hyogo, Japan

• Research Assistant

  • Oct 2004 - Dec 2007

  Research included the study of a large aperture sparce element retrodirective array measurement and demonstration. Collaborated in the design, fabrication, and ISAS supported launch of a retrodirective satellite constellation from the Uchinoura JAXA facility. Design tools included IE3D and ADS. Devices were tested using network analyzers, power meters, and an anechoic chamber. Research included the study of a large aperture sparce element retrodirective array measurement and demonstration. Collaborated in the design, fabrication, and ISAS supported launch of a retrodirective satellite constellation from the Uchinoura JAXA facility. Design tools included IE3D and ADS. Devices were tested using network analyzers, power meters, and an anechoic chamber.



Electro-magnetics Lab, Texas A&M University

• Bryan/College Station, Texas Area

• Research Assistant

  • Apr 2002 - Oct 2004

  Tasks included design, fabrication, and testing microwave systems, antennas, and circuits. A PLL controlled phase conjugation and scaling circuit was designed and implemented into a multi-IF frequency-translating (2.9Ghz Rx/5.8Ghz Tx) retrodirective phased array beam steering transceiver. A large 5.8 GHz CP dual-rhombic loop traveling wave rectifying antenna array was fabricated, tested, and publicly demonstrated at the World Space Congress in Houston, Texas. Designs were achieved using IE3D and ADS simulation tools. Tests were conducted using an HP 8510C network analyzer and an anechoic chamber. Show less



NI (National Instruments)

• United States
• Electrical Equipment Manufacturing
• 700 & Above Employee

• Hardware Engineer Internship

  • Sep 1999 - May 2001

  Designed and implemented the PCI-6036E; a 16 channel 200kS/s 16-bit analog input, 2 channel 10kS/s 16-bit analog output, low-cost, multifunction DAQ PCI board. Tasks included electronic design, pcb layout, technical specification, compliance testing, driver verification, debugging, and manufacture verification testing. All were completed in one co-op term. A test fixture and digital I/O tests were designed and implemented for a new product, the PXI-6115. This test suite and fixture more thoroughly tested digital I/O on DAQ boards and was later expanded across numerous product lines. Show less