Samir DKHISSI

System Validation Engineer at Renault Software Factory
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Location
Greater Toulouse Metropolitan Area, FR

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Franck Da Costa

Durant son stage chez ON Semiconductor en tant que designer digital, Samir a fait preuve d'une très grande application et d'un sérieux remarquable. Très vite intégré à l'équipe, il s'est vu, par son attitude volontaire et engagée, proposer des tâches faisant partie intégrante des projets et activités du département. Celles-ci lui ont permis d'appréhender la globalité du flow de design digital ainsi que les principaux outils des différentes étapes.

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Experience

    • France
    • Motor Vehicle Manufacturing
    • 100 - 200 Employee
    • System Validation Engineer
      • Apr 2021 - Present

      -Preparation, Wiring, Configuration and Maintain FOTA test benches.-FOTA Validation on Bench. (Test campaign creation, execution, analysis, debug )-FOTA Validation on vehicle. (Test campaign creation, execution, analysis, debug on more than 20 ECUs)-Tools: Confluence, JIRA, Can, Doip, Vector CANoe, SILK, Rpdemo, Vnext, RedbendFreelance via Celad.SAS

    • Integration Verification Validation Engineer
      • Nov 2019 - Apr 2021

      - Preparation, Rework, Wiring of Test Bench IVV FACE (Future Architecture for automotive Computing Environment)- Update of Mapping IO file (CAPL)-Debug and development of automation test script (CAPL)-Scripting PYTHON-Patch review-Agile method: SCRUM-Tools: GIT, Confluence, JIRA, Can, Lin, CAPL, Python, AUTOSAR, VECTOR CANoeFreelance via Celad.SAS

    • United States
    • Semiconductor Manufacturing
    • 700 & Above Employee
    • Contractor: System Integrator
      • Jan 2018 - Nov 2019

      Android O and P porting on x86 devices (sw integration, PUPDR, Flashing, Debug)Kernel Patches, Kernel Rebase, External Release generationLauterbach debug (Trace32)Validation FOTA/OTATraining newcomers engineer to Google QA Test (CTS,WTS,ASIT WPTS, VTS)Agile method: SCRUM

    • Contractor: Daily Debug
      • Jan 2017 - Dec 2017

      Intel NDG (New Device Group)Environment: Android Wear System Integration Role: Daily DebuggerTesting Daily Builds to ensure stability of Intel platforms.Analyze crashesAssign and follow tickets (JIRA)Ensure non-regression and deployment of new release on client devicesGoogle QA Testing Lead (CTS, WTS, ASIT WPTS, VTS)Backport linux kernel Upstream security fixes (kernel 4.4 and 3.10)Agile method: SCRUMProducts : Fossil Q, New balance RunIQ, Tag heuer connected Modular 45, Tag heuer connected Modular 41 Show less

    • Contractor: Lab Manager
      • Jan 2012 - Dec 2016

      Lab Management- Equipments and Prototypes Platforms Tracking- Inventory ManagementHardware Support- Hardware reworks (SMD component, wiring out signals for Pnp Measurement)- Troubleshooting, debugging- Flashing Software- JIRA, Excel, Cadence AllegroElectronics Parts Orders- Approval of Purchase follow compliance with Purchasing Policies- Support Team to Identify components needs- Audit purchase

    • France
    • IT Services and IT Consulting
    • 300 - 400 Employee
    • Ingénieur D 'Etudes
      • Mar 2011 - Nov 2019

      Mars à Juillet 2011:Ingénieur Design Digital orienté Vérification Digital. En poste dans les locaux de l'entreprise Freescale Semiconductor à TOULOUSE. Septembre à Décembre 2011: Ingénieur Hardware à DETRACOM 2012 à 2017: Lab Manager à INTEL Toulouse 2017 à 2018: Daily Debug Engineer 2018 à 2019: System Integrator Mars à Juillet 2011:Ingénieur Design Digital orienté Vérification Digital. En poste dans les locaux de l'entreprise Freescale Semiconductor à TOULOUSE. Septembre à Décembre 2011: Ingénieur Hardware à DETRACOM 2012 à 2017: Lab Manager à INTEL Toulouse 2017 à 2018: Daily Debug Engineer 2018 à 2019: System Integrator

    • Semiconductor Manufacturing
    • 1 - 100 Employee
    • Digital Designer (Internship)
      • Apr 2010 - Sep 2010

Education

  • Université Paul Sabatier Toulouse III
    Master, Electronique - Microélectronique
    2008 - 2010

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