Experience

London Startup Week

• United Kingdom
• Events Services
• 1 - 100 Employee

• Vice President System Architecture and Engineering

  • 2021 - Present



Intel Corporation

• United States
• Semiconductor Manufacturing
• 700 & Above Employee

• Engineering manager, Core & Client Design Group

  • Sep 2020 - Present

  Managing HW design teams of high speed & low power ASIC design My group includes Front-End Design, Verification & Power convergence teams Developing Intel’s core new AI and arithmetic modules, driving the core power convergence

• Silicon Engineering Manager

  • Sep 2019 - Sep 2020

  Managing HW design teams of high speed & low power ASIC designResponsible for development, execution and delivery of Intel’s main CPU both to client and server products focusing on low power high performance featuresMy group includes FE (Logic) & BE design teams, Core Integration, Full Chip Timing & Power, DFX, CLK, Thermal density and sign offWorking with architect and business units, understanding customer’s needs, setting product goals and leading timing and power convergence of Intel’s A class CPU Show less

• Design Manager (FE/BE)

  • Apr 2016 - Sep 2019

  Managing R&D cluster of 4 teams at Intel's Big core IPEach team includes FE (RTL) and BE (circuit) designers, working together with architecture and pre / post silicon verification teams to deliver A class products and featuresWe are driving for innovation, out of the box thinking and believe in employee and manager / team development



Intel Corporation

• United States
• Semiconductor Manufacturing
• 700 & Above Employee

• Hardware Design Manager (FE/BE)

  • 2011 - 2016

  Leading a team (RTL & Structural design) at Intel's Haifa development center. My team is in charge of planning and designing Intel core mid level cache unit, taking part in all design phases from initial definitions and studies till mass production. The group makes use of state of the art VLSI design tools, while meeting very challenging timelines, quality, low power, area and speed constraints. Leading a team (RTL & Structural design) at Intel's Haifa development center. My team is in charge of planning and designing Intel core mid level cache unit, taking part in all design phases from initial definitions and studies till mass production. The group makes use of state of the art VLSI design tools, while meeting very challenging timelines, quality, low power, area and speed constraints.



Intel

• Haifa

• Design & Integration Engineer

  • 2006 - 2011

  Hardware designer Owner of various modules / blocks in Intel's processors After few years moved to Integration as section timing owner of EXE cluster Gained extensive knowledge in hardware implementation, flows and methodologies Specialized in the CPU arithmetic calculations (Integer, SIMD) Hardware designer Owner of various modules / blocks in Intel's processors After few years moved to Integration as section timing owner of EXE cluster Gained extensive knowledge in hardware implementation, flows and methodologies Specialized in the CPU arithmetic calculations (Integer, SIMD)



Intel Corporation

• United States
• Semiconductor Manufacturing
• 700 & Above Employee

• Hardware Design Student

  • 2004 - 2006

  Student at Intel Israel design center Haifa Supporting design optimization flows – presto tool, code writing, perl, C++ Student at Intel Israel design center Haifa Supporting design optimization flows – presto tool, code writing, perl, C++