Experience

SiFive

• United States
• Semiconductor Manufacturing
• 400 - 500 Employee

• Senior Engineer

  • Aug 2022 - Aug 2023

  Bengaluru, Karnataka, India • Automated signoff flow development from RTL2GDSII stages of the design for various nodes (ex. 3nm,5nm) automatically. Used dependency graphs to link different design stages while slurm protocol was used to manage compute resources and maximize performance. • Multi-core CPU design targeting >3.1GHz in TSMC n5 technology. • Developed the signoff methodology for TSMC N3E node for both uni and multi-height designs. • Different PPA strategies were used to improve PPA by 15% from N5 to… Show more • Automated signoff flow development from RTL2GDSII stages of the design for various nodes (ex. 3nm,5nm) automatically. Used dependency graphs to link different design stages while slurm protocol was used to manage compute resources and maximize performance. • Multi-core CPU design targeting >3.1GHz in TSMC n5 technology. • Developed the signoff methodology for TSMC N3E node for both uni and multi-height designs. • Different PPA strategies were used to improve PPA by 15% from N5 to N3E technology. Show less



NVIDIA

• United States
• Computer Hardware Manufacturing
• 700 & Above Employee

• ASIC Design Engineer

  • Jul 2019 - Aug 2022

  Bengaluru, Karnataka, India • Optimized the operational run-time of PT-DMSA runs by a factor of N by parallelizing N different collateral generation operation in perl. • Developed a flow that automatically mapped a Logical Netlist(RTL) to Physical Netlist(PD) and generated its Tcl constraints. • Designed Clock Networks for SoC chiplets operating at 3Ghz (5nm Technology) and characterized special clock elements (ex. shaper, trimmers) to ensure linearity. • Synthesis, Place and Route, Clock Tree Planning, STA and… Show more • Optimized the operational run-time of PT-DMSA runs by a factor of N by parallelizing N different collateral generation operation in perl. • Developed a flow that automatically mapped a Logical Netlist(RTL) to Physical Netlist(PD) and generated its Tcl constraints. • Designed Clock Networks for SoC chiplets operating at 3Ghz (5nm Technology) and characterized special clock elements (ex. shaper, trimmers) to ensure linearity. • Synthesis, Place and Route, Clock Tree Planning, STA and Signoff Activities for SOC chiplets operating at 3GHz. Show less



Texas Instruments

• United States
• Semiconductor Manufacturing
• 700 & Above Employee

• Project Trainee

  • May 2018 - Jul 2018

  Banglore IP Design & Verification • Designed a MIPI Slave IP from SPEC to Synthesis using Verilog for low power applications. Designed an automated IP verification framework using python that instantiated a test bench in verilog, activate the DUT based on the test plans, compared the DUT outputs against the golden outputs and generate various coverage metrics. • Designed a framework for divide by N and variable duty cycle glitch free clock Divider. The user could program N and duty cycle… Show more IP Design & Verification • Designed a MIPI Slave IP from SPEC to Synthesis using Verilog for low power applications. Designed an automated IP verification framework using python that instantiated a test bench in verilog, activate the DUT based on the test plans, compared the DUT outputs against the golden outputs and generate various coverage metrics. • Designed a framework for divide by N and variable duty cycle glitch free clock Divider. The user could program N and duty cycle and generate the corresponding synthesized RTL for the design. Show less



CDAC,Noida

• Research Services
• 500 - 600 Employee

• Trainee

  • Jun 2017 - Jul 2017

  Noida Area, India Front End VLSI Design Trainee