Ruben Cohen
VLSI Design Engineer at Valens- Claim this Profile
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Français Native or bilingual proficiency
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Espagnol Native or bilingual proficiency
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Anglais Full professional proficiency
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Hébreu Full professional proficiency
Topline Score
Bio
Credentials
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Python Programming
life michaelNov, 2021- Nov, 2024 -
Career Program
GvahimDec, 2020- Nov, 2024
Experience
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Valens Semiconductor
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Israel
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Semiconductor Manufacturing
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100 - 200 Employee
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VLSI Design Engineer
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Mar 2021 - Present
•Microarchitecture, RTL implementation & Documentation of several blocks from scratch & re-design. Including programming model definitions. Full flow design in Verilog, Lint, CDC, verification support (Cadence Simvision) & integration. •RTL legacy blocks enhancements •Full PHY integrator with synthesis ramp-up & flow. •Working closely with other VLSI teams - architecture, verification, DFT, FPGA, BE, on site & abroad. •Microarchitecture, RTL implementation & Documentation of several blocks from scratch & re-design. Including programming model definitions. Full flow design in Verilog, Lint, CDC, verification support (Cadence Simvision) & integration. •RTL legacy blocks enhancements •Full PHY integrator with synthesis ramp-up & flow. •Working closely with other VLSI teams - architecture, verification, DFT, FPGA, BE, on site & abroad.
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Israel Defense Forces
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Israel
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Armed Forces
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700 & Above Employee
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Infantry Soldier
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2012 - 2014
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Education
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Tel Aviv University
Bachelor of Science - BS, BSc Electrical and Electronics Engineering -
The Hebrew University
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Lycée International des Pontonniers
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Lycée Français de Barcelone