Experience

Sankalp Semiconductor

• United States
• Semiconductor Manufacturing
• 300 - 400 Employee

• Senior Analog Layout Engineer

  • Jan 2021 - Present

• Analog Layout Engineer

  • Sep 2017 - Jan 2021

  Work experience* Experience in Analog & mixed signal layout design.* Worked on multiple projects, complete cycle from area estimation, floor plan to tape out.* Worked on TSMC3nm, TSMC 5nm, TSMC16nm,TSMC7nm, intel10nm, gpdk45nm technology.*worked on floorplan, placement & routing of Analog blocks.*Worked on EM/IR issues in Finfet.*Worked on HV errors.*worked on ESD and latch up checks.*worked on extraction for layouts.*knowledge of antenna effect, EM, parasitic, ESD, Latch up, WPE, LOD, matching and shielding.*physical verification check: DRC, LVS, Density, ERC, MRC, Antenna check, DFM,ESD checks.Worked majorly on following sub-blocks:BGR, LDO, TX, RX, DLL, Vref, comparator, VCO, level shifters, Serializers , high speed blocks. IP level work done for LDO, RX , TXRX blocks.VLSI tools:Layout design tool:- Cadence Virtuoso xl/vxl/exl, Genesys.verification tool:- Assura, Calibre, ICV, CPDS .programming language :- C ,PERL, Skill.platform:- Linux , KDE , Windows.