Rohit kapur

Senior Principal Software Engineer at Raytheon Technologies
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Contact Information
us****@****om
(386) 825-5501
Location
US

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Experience

  • Raytheon Technologies
    • Aberdeen Proving Ground, Maryland, United States
    • Senior Principal Software Engineer
      • 2020 - Present

      Senior Principal Software Engineer (2022 to 2016) • Working two concurrent APX-119 programs fixing software defects. Newer APX-119 software defects were fixed in C and C++ running on the Safety Certified VxWorks 7.0 RTOS. Legacy APX-119 software defects were fixed in C running on Integrity RTOS. • Lead a team of 5 software engineers to port legacy APX-119 Transponder software running on a two-card solution, RL4 Single Board Computer using Integrity RTOS and interfacing to a Mode 5 hardware-ready Improved IFF Signal Processor (I2SP) card capable of generating replies at 1090MHz to various IFF interrogations at 1030 MHz, into C and C++ running on a CTM card consisting of the Xilinx’s Znyq 7000 SoC using WindRiver’s Safety Certified VxWorks 7 RTOS. Obtained a full TSO using DO-178C for the new APX-119.

  • Raytheon Technologies
    • Aberdeen Proving Ground, Maryland, United States
    • Principal Software Engineer
      • 2013 - 2019

      • Lead a team of 2 software engineers on a spiral effort to add new ARINC 429 Label functionality into the Digital Control Panel (DCP), and to add new functionality into various existing screens on the DCP. Obtained a minor TSO Certification for the software using DO-178B. Code was developed in C using Altera’s Nios II SoC. • Managed two concurrent software programs leading a team of 4 software engineers to add AIMS 03-1000B updates into the DCP, and to obtain full DO-178B TSO Certification for the DCP. • Lead a team of 5 software engineers to add the ADS-B Out functionality into the DCP.

    • United States
    • Aviation and Aerospace Component Manufacturing
    • 700 & Above Employee
    • Senior Software Engineer II
      • 2006 - 2012

      • Lead a team of 6 software engineers in the development of a new IFF product, the Digital Control Panel (DCP). Software was designed in C using Altera’s Nios II System On A Chip (SoC) Embedded FPGA processor. Duties consisted of software technical development, managing day-to-day activities for entire software team, managing cost and schedule of entire software effort using EVMS, and reporting monthly status to upper management using EVMS. • Updated legacy APX-119’s System Processor software running on the RL4 Single Board computer to design device drivers for the Spansion’s Flash chip, and Holt Inc.’s ARINC 429 devices existing on the I2SP card that interfaces with the Single Board Computer. Also updated System Processor Software to reprogram software/firmware images stored on the I2SP card using either an ARINC 615-3 or MLVS data loaders via the 429 or the 1553 interfaces. Created Built-In-Test software that runs on the Analog Device’s 2191 DSP chip existing on the I2SP board that interfaces with the System Processor Software.

    • Senior Software Engineer I
      • 2001 - 2006

      • Designed an APX-114 Interrogator waveform software using UML principles and CORBA that can be loaded into any Software Communications Architecture (SCA) compliant Joint Tactical Radio capable of interrogating various IFF Modes. Interrogator waveform was created using C++, ORBExpress, and VxWorks 5.5.1. Also created an Interrogation Control GUI in JAVA to set Schedule data and send data to the waveform using JAVA’s ORB. • Designed GUI screens using Visual Basic 6.0 for the Status Display component of a Precision Runway Monitor Air Traffic Control System. Some code was written in C++.

    • Software Engineer II
      • 1999 - 2001

      • Designed a BIOS, a Board Support Package, and an AMD79C940 ethernet driver for a 386EX microcontroller Red File Server for a Multi-Mission Advance Tactical terminal.

  • Orbital Sciences Corporation
    • Germantown, Maryland
    • Software Engineer
      • Feb 1998 - Oct 1999

  • CACI Federal
    • Dayton, Ohio
    • Software Engineer
      • Feb 1996 - Oct 1998

    • Programmer Analyst
      • Sep 1994 - Feb 1996

Education

  • Johns Hopkins University
    MSCS, Part-Time Computer Science Program
    1999 - 2005
  • Virigina Tech University
    MSEE, Electrical Engineering
    1991 - 1993
  • West Virginia University
    BSEE, Electrical Engineering
    1987 - 1991

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