Experience

Speedata.io

• Israel
• Semiconductors
• 1 - 100 Employee

• Senior Verification Engineer

  • Mar 2023 - Present

  Block and cluster owner. Develop UVM TB from scratch with vManager. Working as part of a global verification team. Block and cluster owner. Develop UVM TB from scratch with vManager. Working as part of a global verification team.



AST SpaceMobile

• United States
• Telecommunications
• 200 - 300 Employee

• Senior Verification Engineer

  • Oct 2021 - Jan 2023

  Define and manage AST verification infrastructure. Write UVM block testbench include reuse on Full Chip Define and manage AST verification infrastructure. Write UVM block testbench include reuse on Full Chip



Samsung Israel R&D Center - SIRC

• Israel
• Computers and Electronics Manufacturing
• 300 - 400 Employee

• Senior Verification Engineer

  • Oct 2007 - Sep 2021

  Write test plans and develop SVTB and UVM testbenches. Automate checkers flow using CSV format for designer's easy usage. Write test plans and develop SVTB and UVM testbenches. Automate checkers flow using CSV format for designer's easy usage.



LSI, an Avago Technologies Company

• Semiconductor Manufacturing
• 700 & Above Employee

• Verification Engineer

  • 2005 - 2007

  Develop Specman and vManager environments. Programming with eRM methodology. Develop Specman and vManager environments. Programming with eRM methodology.



Marvell Semiconductor

• 1 - 100 Employee

• Verification Engineer

  • 2001 - 2004

  Verification and validation of ASIC / VLSI switch devices. Define and develop environment testing in unit and full chip level, Verification and validation of ASIC / VLSI switch devices. Define and develop environment testing in unit and full chip level,