Experience

Numem

• United States
• Semiconductors
• 1 - 100 Employee

• VP of Engineering

  • Apr 2021 - Present

  System Architecture, Digital Design and Verification System Architecture, Digital Design and Verification



Broadcom

• United States
• Semiconductor Manufacturing
• 700 & Above Employee

• R&D Management

  • May 2005 - Mar 2021

  • SOC Verification for Wireless LAN Connectivity Combo Chips • Project Management of Cross-functional and cross-site teams • Managed Peripheral IP Development Team in Central Engineering • Lead USB 3.1 Gen1/Gen2 Controller and Physical layer IP development • Responsible for managing Pre-and Post-silicon validation of IPs such as USB Controllers, USB/PCIe/SATA multiprotocol Physical layer module, DDR and OTP Controllers • Verification lead for the USB 3.1 Gen1/Gen2 IP, involving development of in-house verification components, integrating third-party VIPs and maintain test plans, functional and code coverage metrics • Design and Development of RTL and Bus Functional Models of MIPI SLIMBus (Serial Low-power Inter-chip Media Bus) • Design Development and Maintenance of OTP (One-time programmable) Memory Controller for multiple process nodes • Architecture of OTP ROM Evaluation and Qualification Vehicle (Hardware and Software) • Architect, Design and coordinate tape-out of Process Technology validation Test chips • Design and implementation 7-port Register file • Design of Mobile Pixel Link (MPL) PHY IP Show less



STMicroelectronics Inc.

• Phoenix, Arizona, USA ; San DIego, CA, USA

• Senior Principal Engineer

  • Nov 1994 - May 2005

  Data Storage Division, STMicroelectronics Inc., San Diego, CA / Phoenix, AZ • Implementation of Cache sub-system extension to a C++ based architectural simulator (CHESS) of ST100 DSP • Design implementation (VHDL) and validation of Data Stream Engine for a LCC (Low Cost Read-Write Channel) • LCC Digital Back-End subsystem integration and Prototyping for SNR and Performance Analysis • Responsible and lead the effort of Functional Verification of Channel Design and OpenVera based Verification Platform Design using RVM components Central R&D, STMicroelectronics Inc., San Diego, CA / Phoenix, AZ • Functional Verification of Network Packet Search Engine (NPSE) – an algorithmic implementation of prefix search pipeline engine • System level simulation and Performance analysis of NPSE in Intel SDK platform for Network Processors using IPv4 Forwarding application NVG, STMicroelectronics Inc., San Diego, CA / Phoenix, AZ • Team lead for the functional verification and compatibility validation of Super scalar x86 compatible microprocessor for Embedded System Applications • Responsible for the emulation based functional verification of Super scalar x86 compatible microprocessor designs • Contributed to Low power design implementation using extensive clock gating and mixed threshold (Low Vt and High Vt for lower leakage) design methodology • Responsible for TLB (Translation Look-aside Buffer) functional Verification, Timing Analysis of processor Cache memory sub system. • Involved in the micro-architecture debug, post-silicon validation of processor designs Show less



STMicroelectronics Spa.

• Milan Area, Italy

• Senior CAD Engineer

  • Feb 1989 - Oct 1994

  Central R&D/ PPG, STMicroelectronics Spa., Agrate Brianza (MI), ITALY • Design and Development of EARLY, a delay evaluation and back annotation system, widely used in the company as a de facto sign off tool, for the evaluation of Cell delays taking into account Rise/Fall transition time of signal transitions and RC interconnect load. • Design and development of Clock tree analysis and estimation tool that analyzes the propagation of clocks and required buffering. • Development of ATE flows to generate a complete ATE specific (Sentry 21/J971/J973) test program based on functional simulation vectors • Development of a Front-End Hierarchical Lint Design Rule Checker (HDRC) for the checking of various design violations. This involved design of a new user-friendly language for the custom specification of design rules. • Integration and interface of user programmable of Module Generators design development system (design-kits) for semi-custom designs Show less



Semiconductor Complex Ltd

• Semiconductors
• 1 - 100 Employee

• Member Technical Staff

  • Aug 1987 - Feb 1989

  • Member of CAD tools development team. Contributed to the development of fully hierarchical design entry package, as a part of developing workstation based IC design system (BEACON). • Involved in the design and development of Integrated Design Database for the BEACON system. Developed Graphics interface to the Design Data for creating Library cells. • Member of CAD tools development team. Contributed to the development of fully hierarchical design entry package, as a part of developing workstation based IC design system (BEACON). • Involved in the design and development of Integrated Design Database for the BEACON system. Developed Graphics interface to the Design Data for creating Library cells.