Experience

Rivos Inc.

• United States
• Computer Hardware Manufacturing
• 100 - 200 Employee

• Physical Design Engineer

  • Jun 2022 - Present

  Austin, Texas, United States



NVIDIA

• United States
• Computer Hardware Manufacturing
• 700 & Above Employee

• Principal Engineer

  • May 2020 - Jun 2022

  California, United States I am worked as a lead physical designer on IR/EM convergence, floor planning, design planning and place and route. I have worked on the next gen client GPU and switch chips for server applications. As a full chip IR/EM lead worked with owners from different teams and sites for PNR/ECO flows enhancements, work-model, methodology and recipe improvements to achieve smooth IR/EM convergence. Created and implemented floorplans of 3 client GPU chips. Carried out design planning of a routing… Show more I am worked as a lead physical designer on IR/EM convergence, floor planning, design planning and place and route. I have worked on the next gen client GPU and switch chips for server applications. As a full chip IR/EM lead worked with owners from different teams and sites for PNR/ECO flows enhancements, work-model, methodology and recipe improvements to achieve smooth IR/EM convergence. Created and implemented floorplans of 3 client GPU chips. Carried out design planning of a routing challenged chiplet and provided high quality (managing pin densities and path detours) top-down collateral for partitions enabling timing & layout convergence. Also, worked on PNR for several partitions (~3GHz) and efficiently converged them for tapeout. Implemented various scripts and recipes and actively shared them within and across projects. I actively mentored many engineers and ramped them on design, flow, methodology, IR/EM, etc. Collaborating with the design automation team for tools, flows and methodology improvements. Show less



Intel Corporation

• United States
• Semiconductor Manufacturing
• 700 & Above Employee

• SoC Design Engineer/Full-chip Timing/Floorplan Owner/Syn-APR (Senior Staff Eng)

  • Jan 2018 - May 2020

  Hillsboro, Oregon Define top-down and bottom-up backend design, integration and timing/physical verification methodology. Working on full-chip level floorplan and timing for cores. Research and development of novel design approaches for efficient convergence while meeting PPA goals. Large partition syn and apr for design convergence . Mentoring junior engineers.

• SoC Design Engineer (Senior Staff Eng)

  • Apr 2012 - Dec 2017

  Hillsboro, OR Full chip integration -- floor planning, design and implementation of high speed global fabrics including cache coherent and chassis fabrics. Physical design planning and integration methodology for efficient design convergence. Full chip timing analysis and convergence. Layout expertise especially of 10/14/22 nm process nodes. Cell based design -- Synthesis and APR flow development and execution. Custom implementation flow development and automation for final design convergence. Extensive… Show more Full chip integration -- floor planning, design and implementation of high speed global fabrics including cache coherent and chassis fabrics. Physical design planning and integration methodology for efficient design convergence. Full chip timing analysis and convergence. Layout expertise especially of 10/14/22 nm process nodes. Cell based design -- Synthesis and APR flow development and execution. Custom implementation flow development and automation for final design convergence. Extensive block/partition implementation (syn and apr) experience.

• Software Engineer/Researcher

  • Apr 2009 - May 2012

  Hillsboro, OR Research and development of DFM tools and engines. Specialized in development and implementation of efficient geometric fill algorithms (dummification flows) to meet complex design rules of 10nm/14nm/22nm processes.



Intel Corporation

• United States
• Semiconductor Manufacturing
• 700 & Above Employee

• Design Engineer -- Summer Intern

  • May 2007 - Aug 2007

  Austin, Texas Area Designed and implemented clock distribution for IO blocks of a 45nm SoC. Designed and implemented power gating circuit to meet static and dynamic IR specifications. Performed characterization of slew rate control circuit to check if it met under-shoot/over-shoot specifications.



Mitsubishi Electric Research Laboratories

• United States
• Research
• 1 - 100 Employee

• Summer Inten

  • May 2006 - Aug 2006

  Cambridge, Massachusetts Low power implementation of multi-band orthogonal frequency division multiplexing (MBOFDM) ultra- wide band (UWB) radio receiver. Implemented a low power Viterbi Decoder using dynamic voltage scaling. Implemented an adaptive sliding block Viterbi decoder in MATLAB



Tejas Networks

• India
• Telecommunications
• 700 & Above Employee

• R&D Engineer

  • Sep 2004 - Dec 2004

  Bangalore, India Performed board design and FPGA coding for STM4 products. Designed a tester card for the system control unit card for STM4 equipment.