Raja S

Senior Lead Engineer at Sankalp Semiconductor
  • Claim this Profile
Contact Information
us****@****om
(386) 825-5501
Location
India, IN

Topline Score

Topline score feature will be out soon.

Bio

Generated by
Topline AI

You need to have a working account to view this content.
You need to have a working account to view this content.

Experience

    • United States
    • Semiconductor Manufacturing
    • 300 - 400 Employee
    • Senior Lead Engineer
      • Jan 2019 - Present

    • India
    • IT Services and IT Consulting
    • 700 & Above Employee
    • Technical Lead
      • May 2011 - Present

      Currently working in INDIA and employed at a leading organization L&T Technology Services, A subsidiary of a 12b$ company Larsen and Toubro Limited. I work for a USB Host controller(xHCI) IP Core product development. We as a team work on developing High serial interface protocols IP products like USB Device controllers, USB HUB, USB Host controller (xHCI). Support USB3 and USB2. In process We as a team do RTL Design for intel's xHCI specifications, verification, do Lint, CDC, synthesis and validate in FPGA. I am part of architecture design, RTL design, defect fix, lint check, synthesis, Validating IP in FPGA. Thanks, Raja S Show less

    • India
    • IT Services and IT Consulting
    • 700 & Above Employee
    • Member Technical Staff
      • Jun 2010 - May 2011

      RTL Design for custom requirement from an aerospace customer France. Worked from micro architeture development and RTL design. Design verified with verilog environment and validated with FPGA. RTL Design for custom requirement from an aerospace customer France. Worked from micro architeture development and RTL design. Design verified with verilog environment and validated with FPGA.

    • Appliances, Electrical, and Electronics Manufacturing
    • 1 - 100 Employee
    • FPGA Design Engineer
      • Jul 2008 - Jun 2010

      RTL Design and development for custom requirements. Validated with FPGA. Worked as team with Board Designers and Firmware development engineers. RTL Design and development for custom requirements. Validated with FPGA. Worked as team with Board Designers and Firmware development engineers.

    • India
    • Education Administration Programs
    • 100 - 200 Employee
    • Associate Consultant
      • Apr 2007 - Jun 2008

      Trainer for Digital Fundamanetals, Verilog, Lint check and Synthesis. Trainer for Digital Fundamanetals, Verilog, Lint check and Synthesis.

Education

  • Shanmugha Arts, Science, Technology and Research Academy
    Bachelor of Technology (B.Tech.), Electronics and Communications Engineering
    2003 - 2006

Community

You need to have a working account to view this content. Click here to join now