Raghu Garikapaty
ASIC DV at RiseEdge- Claim this Profile
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Bio
David Du
Raghu worked as a DV engineer for our team across two projects over many years. During his time, he mainly focused on UVM Block Level DV of our external interfaces, but he also helped us in many other areas such as: top level RTL & GLS verification, code coverage analysis, and ramping up other new engineers. He was easy to work with and the blocks he worked on came back from the fab with no critical bugs. When the need came up, he was able to quickly jump to code coverage analysis and ramp up on our process and flow. He received daily input waiver files from different designers and would produce the reports needed for our customer. I would not hesitate to work with Raghu again in the future.
Shoumik Maiti
Raghu was responsible for DFT implementation for a complex interface IP subsystem while working in the team that I managed. He worked with the customer to understand the requirements and architected a solution using state-of-the-art compression techniques. Raghu developed the DFT insertion scripts from scratch and achieved target ATPG coverage. Raghu also helped develop scan mode timing constraints and set up gate-level pattern simulations. Raghu completed all the work on time and ensured that the customer could seamlessly integrate the subsystem in their SoC.
David Du
Raghu worked as a DV engineer for our team across two projects over many years. During his time, he mainly focused on UVM Block Level DV of our external interfaces, but he also helped us in many other areas such as: top level RTL & GLS verification, code coverage analysis, and ramping up other new engineers. He was easy to work with and the blocks he worked on came back from the fab with no critical bugs. When the need came up, he was able to quickly jump to code coverage analysis and ramp up on our process and flow. He received daily input waiver files from different designers and would produce the reports needed for our customer. I would not hesitate to work with Raghu again in the future.
Shoumik Maiti
Raghu was responsible for DFT implementation for a complex interface IP subsystem while working in the team that I managed. He worked with the customer to understand the requirements and architected a solution using state-of-the-art compression techniques. Raghu developed the DFT insertion scripts from scratch and achieved target ATPG coverage. Raghu also helped develop scan mode timing constraints and set up gate-level pattern simulations. Raghu completed all the work on time and ensured that the customer could seamlessly integrate the subsystem in their SoC.
David Du
Raghu worked as a DV engineer for our team across two projects over many years. During his time, he mainly focused on UVM Block Level DV of our external interfaces, but he also helped us in many other areas such as: top level RTL & GLS verification, code coverage analysis, and ramping up other new engineers. He was easy to work with and the blocks he worked on came back from the fab with no critical bugs. When the need came up, he was able to quickly jump to code coverage analysis and ramp up on our process and flow. He received daily input waiver files from different designers and would produce the reports needed for our customer. I would not hesitate to work with Raghu again in the future.
Shoumik Maiti
Raghu was responsible for DFT implementation for a complex interface IP subsystem while working in the team that I managed. He worked with the customer to understand the requirements and architected a solution using state-of-the-art compression techniques. Raghu developed the DFT insertion scripts from scratch and achieved target ATPG coverage. Raghu also helped develop scan mode timing constraints and set up gate-level pattern simulations. Raghu completed all the work on time and ensured that the customer could seamlessly integrate the subsystem in their SoC.
David Du
Raghu worked as a DV engineer for our team across two projects over many years. During his time, he mainly focused on UVM Block Level DV of our external interfaces, but he also helped us in many other areas such as: top level RTL & GLS verification, code coverage analysis, and ramping up other new engineers. He was easy to work with and the blocks he worked on came back from the fab with no critical bugs. When the need came up, he was able to quickly jump to code coverage analysis and ramp up on our process and flow. He received daily input waiver files from different designers and would produce the reports needed for our customer. I would not hesitate to work with Raghu again in the future.
Shoumik Maiti
Raghu was responsible for DFT implementation for a complex interface IP subsystem while working in the team that I managed. He worked with the customer to understand the requirements and architected a solution using state-of-the-art compression techniques. Raghu developed the DFT insertion scripts from scratch and achieved target ATPG coverage. Raghu also helped develop scan mode timing constraints and set up gate-level pattern simulations. Raghu completed all the work on time and ensured that the customer could seamlessly integrate the subsystem in their SoC.
Experience
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RiseEdge
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United States
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Semiconductor Manufacturing
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1 - 100 Employee
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ASIC DV
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Sep 2019 - Present
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Synopsys Inc
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United States
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Software Development
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700 & Above Employee
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ASIC Design and Verification
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May 2018 - Aug 2019
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Qualcomm
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United States
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Telecommunications
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700 & Above Employee
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Sr. Staff Verification Engineer
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Nov 2015 - May 2018
UVM Testbench Architect, Experience in UVC development. Developed Constrained-Random Stimulus, Coverage Metrics driven Verification Sign-off. Experience in Writing Assertions, UVC configuration, Scoreboards & Co-Simulation. Experience in Mixed-Signal Macros, PMIC and Blue-Tooth Radios Integration to SOC. Experience in Blue-Tooth RX, TX Datapath verification at SOC. Developed PTA UVC and Verified blue-tooth, WiFi Co-existence. Ported IP Level BTC, BTLE, EDR packet Blue-tooth tests to SOC. Hands-On Experience in Low-Power Sign-Off, AMS Simulations. Experience in IP Integration and RTL design. UVM Testbench Architect, Experience in UVC development. Developed Constrained-Random Stimulus, Coverage Metrics driven Verification Sign-off. Experience in Writing Assertions, UVC configuration, Scoreboards & Co-Simulation. Experience in Mixed-Signal Macros, PMIC and Blue-Tooth Radios Integration to SOC. Experience in Blue-Tooth RX, TX Datapath verification at SOC. Developed PTA UVC and Verified blue-tooth, WiFi Co-existence. Ported IP Level BTC, BTLE, EDR packet Blue-tooth tests to SOC. Hands-On Experience in Low-Power Sign-Off, AMS Simulations. Experience in IP Integration and RTL design. Show less
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CSR
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United Kingdom
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Semiconductor Manufacturing
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700 & Above Employee
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Staff verificaiton Engineer
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Jul 2011 - Aug 2015
Lead Verification of GPS chips. Verification of ARM subsytems, DSP subsytems Low-power verification using AMS modeling. Active Role in FPGA activity. Flash and SQIF verification in OVM/UVM. Lead Verification of GPS chips. Verification of ARM subsytems, DSP subsytems Low-power verification using AMS modeling. Active Role in FPGA activity. Flash and SQIF verification in OVM/UVM.
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STMicroelectronics
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Switzerland
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Semiconductor Manufacturing
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700 & Above Employee
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Sr. Staff Engineer
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Jan 1999 - 2011
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Education
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National Institute of Technology Warangal
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