Experience

NVIDIA

• United States
• Computer Hardware Manufacturing
• 700 & Above Employee

• ASIC Design Engineer

  • Nov 2023 - Present

  Austin, Texas, United States



Cornell University

• United States
• Higher Education
• 700 & Above Employee

• Graduate Research Assistant, M3 Architecture Research Group

  • Jan 2023 - May 2023

  Ithaca, New York, United States • Investigated Processing in Memory in different memory technologies (DRAM, SRAM, HBM) and layers in the memory hierarchy (cache, main memory) as a Semiconductor Research Corporation scholar. • Presented Processing in Memory papers and identified the results-driven ideas for a virtualization publication.

• Graduate Teaching Assistant, ECE 4750 / 5740 - Computer Architecture

  • Aug 2022 - Dec 2022

  Ithaca, New York, United States • Led a team of 5+ Teaching Assistants to grade Verilog RTL labs on Processor, Memory, and Network Design, spanning RTL Design, RTL Verification, and RTL Code Quality for 100+ students. • Graded quizzes and exams focusing on pipeline diagrams and assembly problems and graduate position papers on RISC-V and advanced caching techniques.

• Graduate Research Assistant, Batten Research Group

  • Aug 2021 - Oct 2022

  Ithaca, New York, United States • Accelerated genomics on 3 architectures as the NSF Panorama Computer Architecture PhD lead. • Guided 4+ Master of Engineering (MEng) student projects on genomics and Machine Learning acceleration on Xilinx FPGA's via RTL design entry in Verilog and High Level Synthesis and FPGA synthesis via TCL. • Presented the first Panorama workshop on vectorizing genomics applications for the Processing in-SRAM chip "Associative Processing Unit" by startup GSI. Tutorial was used by 20+ students to… Show more • Accelerated genomics on 3 architectures as the NSF Panorama Computer Architecture PhD lead. • Guided 4+ Master of Engineering (MEng) student projects on genomics and Machine Learning acceleration on Xilinx FPGA's via RTL design entry in Verilog and High Level Synthesis and FPGA synthesis via TCL. • Presented the first Panorama workshop on vectorizing genomics applications for the Processing in-SRAM chip "Associative Processing Unit" by startup GSI. Tutorial was used by 20+ students to start their Processing-in-Memory research. • Achieved a 3.9x GPU speed-up for sequence alignment algorithm Smith-Waterman scaled to 128 cores on the HammerBlade manycore architecture.



Microsoft

• United States
• Software Development
• 700 & Above Employee

• Contracting Hardware Design Engineer

  • May 2020 - Aug 2020

  Redmond, Washington

• Research Intern

  • Jan 2020 - Apr 2020

  Redmond, Washington • Built a real-time performance monitoring hardware for an NLP Machine Learning FPGA Architecture. • Profiled arithmetic, memory, and control flow microoperations to breakdown hardware execution and its fraction relative to stalls. Exposed profiling library to developers to support function-level profiling of microoperation execution. • Transferred data from its origin in the registers of FPGA logic cells to a FIFO in BRAM to a DRAM partition exposed to the host CPU. Used DMA to offload… Show more • Built a real-time performance monitoring hardware for an NLP Machine Learning FPGA Architecture. • Profiled arithmetic, memory, and control flow microoperations to breakdown hardware execution and its fraction relative to stalls. Exposed profiling library to developers to support function-level profiling of microoperation execution. • Transferred data from its origin in the registers of FPGA logic cells to a FIFO in BRAM to a DRAM partition exposed to the host CPU. Used DMA to offload bulk DRAM transfer of profiling data to CPU. • Achieved reliable data transfer via Memory-Mapped AXI interfaces and Clock-Domain-Crossing between the FPGA logic clock domain and DRAM clock domain via a Dual Clock Asynchronous FIFO in BRAM.



University of Virginia

• United States
• Higher Education
• 700 & Above Employee

• Research Intern- Virginia Microelectronics Consortium

  • May 2019 - Aug 2019

  Charlottesville, Virginia • Emulated DRAM on FPGA starting with C++ DRAM simulator DRAMSim and using High-Level-Synthesis for RTL synthesis. Wrote Verilog to model more accurate DRAM functionality and achieve FPGA optimization. • Emulated DRAM on FPGA served for modification with Processing in Memory logic to study different Processing in Memory configurations.