Prafulla Galphade

Program Management Director at Cadence Design Systems (India) Pvt. Ltd.
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Contact Information
us****@****om
(386) 825-5501
Location
Bengaluru, Karnataka, India, IN

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Experience

    • Program Management Director
      • Jul 2023 - Present

      Bengaluru, Karnataka, India

    • Senior Principal Program Manager
      • Apr 2019 - Jul 2023

      Bangalore Leading Project Management functions at Cadence Design Systems (I) Pvt Ltd, India, for IP Group having responsibilities – • Customer Projects execution and delivery o SOW Development and ECO’s o External and Internal Communication o Schedule Planning & Progress Tracking o Ensuring Receivables and Deliverables. o Problem solving and Issue resolutions • R&D Development o MRD and PRD reviews o Phase Gate Reviews o Project Planning and Execution o Schedule… Show more Leading Project Management functions at Cadence Design Systems (I) Pvt Ltd, India, for IP Group having responsibilities – • Customer Projects execution and delivery o SOW Development and ECO’s o External and Internal Communication o Schedule Planning & Progress Tracking o Ensuring Receivables and Deliverables. o Problem solving and Issue resolutions • R&D Development o MRD and PRD reviews o Phase Gate Reviews o Project Planning and Execution o Schedule Planning & Progress Tracking o Ensuring Product Quality • Project Management Office and Operations o Project Resource, Cost and Schedule Estimations o Resource and Schedule Planning o Vendor Management o Improvements and Enhancements in PMO Systems and KPI’s. o Training and support contact for internal/External tools e.g. Atlassian JIRA. • People Manager o Leading a team of Program Managers responsible for day to day execution of projects, resource management, schedule management, cross domain integration for projects and other program management tasks.

    • India
    • Business Consulting and Services
    • 1 - 100 Employee
    • PMTS
      • Apr 2016 - Mar 2019

      Bangalore Managed program for multiple Memory projects, was responsible for tasks like Resource plan, outsource resource management, Interactions with global teams etc. Functioning as a Layout Tech Lead, responsible for on time deliveries of all the Memory IP from Bangalore. Provided directions and guidelines to Layout Engineers in the team. Functioned as Memory CAD Manager; responsible for Memory CAD at India. Recruited 80+ young Engineers from Various Engineering Colleges across India through… Show more Managed program for multiple Memory projects, was responsible for tasks like Resource plan, outsource resource management, Interactions with global teams etc. Functioning as a Layout Tech Lead, responsible for on time deliveries of all the Memory IP from Bangalore. Provided directions and guidelines to Layout Engineers in the team. Functioned as Memory CAD Manager; responsible for Memory CAD at India. Recruited 80+ young Engineers from Various Engineering Colleges across India through Campus drives. Show less

    • SMTS
      • Feb 2015 - Mar 2016

      Bangalore

    • United States
    • Semiconductor Manufacturing
    • 700 & Above Employee
    • Component Design Enginner
      • Apr 2008 - Feb 2015

      Bangalore Layout Lead in Intel Custom Foundry Group, leading Layout teams on foundation IP projects.. As a Layout Lead responsible for on time Layout releases, meeting quality expectations Managing Layout activities i.e. scheduling, Floor Planning, leaf cell design & top-level integration, Reliability Verification etc. Mentorship, providing directions and guiding Layout Engineers in the group were the primary tasks. Did RTL coding for various IP’s. Undertaken projects on Memory Compiler, DDR,… Show more Layout Lead in Intel Custom Foundry Group, leading Layout teams on foundation IP projects.. As a Layout Lead responsible for on time Layout releases, meeting quality expectations Managing Layout activities i.e. scheduling, Floor Planning, leaf cell design & top-level integration, Reliability Verification etc. Mentorship, providing directions and guiding Layout Engineers in the group were the primary tasks. Did RTL coding for various IP’s. Undertaken projects on Memory Compiler, DDR, and Microprocessor, IO’s LDO, Thermal Sensors etc. Show less

    • Semiconductor Manufacturing
    • 1 - 100 Employee
    • Mask Designer
      • Jul 2006 - Apr 2008

      Bengaluru, Karnataka, India Worked on projects on SRAM Memory Compiler and Custom Test Chips as a Mask Designer. As a layout lead, guided other Layout Engineers & provided on job training to new entrant Engineers.

    • Germany
    • Semiconductor Manufacturing
    • 700 & Above Employee
    • Technical Consultant
      • Aug 2005 - Jul 2006

      Bengaluru, Karnataka, India Started career as Memory Layout Engineer worked on various memory compiler blocks.

    • FAE
      • May 2005 - Aug 2005

      Field Application Engineer

    • Higher Education
    • 1 - 100 Employee
    • College Lecturer
      • Jul 2003 - May 2005

      Bhopal, Madhya Pradesh, India Imparting theoretical and practical training to students in “VLSI Design” and “Digital Circuits and Systems”. Established VLSI Design Lab for the Institute. Guided numerous projects VLSI design for academic purposes.

Education

  • Sardar Vallabhbhai National Institute of Technology, Surat
    M Tech, VLSI Design
    2009 - 2011
  • Nagpur University
    M BA, Mkt & Fin
    1998 - 2000
  • Nagpur University
    BE, Electronics
    1993 - 1997
  • Soft Polynomials

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