Peter Bjeletich
Director of Engineering and Automation Systems at Otsuka America, Inc.- Claim this Profile
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Bio
Henry Chao
Peter helped drive Intel's and Numonyx's NOR Flash development activities as the frontend integration team lead. In a very short time from when he joined the team, he was able to quickly absorb the complexities of the Flash process and take command of a focus team overseeing a large chunk of the process flow. A diligent and self-driven engineer, he helped identify new scaling techniques/architectures and resolved key frontend issues with minimal supervision, great discipline and detailed organization, all while maintaining excellent rapport with those he worked with. I found Peter to be a invaluable member of my team and strongly recommend him to any company looking for an excellent engineer able to quickly learn and drive critical activities.
Steven Soss
I had the pleasure of working with Peter to develop the 45nm self-aligned flash architecture for Intel and later Numonyx. During the time I worked with Peter, he was the front-end integration lead. Peter exhibited creativity as well as the ability to lead his integration team to meet the challenges of a new architecture. Though his leadership, the team developed several patentable scaling "tricks" and was able to stay within the existing capital equipment set to keep costs for the flash technology in line. I found Peter to be able to both motivate his team (process engineering and integration engineering) as well as work well with outside teams such as device, lithography, and product engineering teams. I can easily recommend Peter as someone who can innovate as well as translate a vision to his team.
Henry Chao
Peter helped drive Intel's and Numonyx's NOR Flash development activities as the frontend integration team lead. In a very short time from when he joined the team, he was able to quickly absorb the complexities of the Flash process and take command of a focus team overseeing a large chunk of the process flow. A diligent and self-driven engineer, he helped identify new scaling techniques/architectures and resolved key frontend issues with minimal supervision, great discipline and detailed organization, all while maintaining excellent rapport with those he worked with. I found Peter to be a invaluable member of my team and strongly recommend him to any company looking for an excellent engineer able to quickly learn and drive critical activities.
Steven Soss
I had the pleasure of working with Peter to develop the 45nm self-aligned flash architecture for Intel and later Numonyx. During the time I worked with Peter, he was the front-end integration lead. Peter exhibited creativity as well as the ability to lead his integration team to meet the challenges of a new architecture. Though his leadership, the team developed several patentable scaling "tricks" and was able to stay within the existing capital equipment set to keep costs for the flash technology in line. I found Peter to be able to both motivate his team (process engineering and integration engineering) as well as work well with outside teams such as device, lithography, and product engineering teams. I can easily recommend Peter as someone who can innovate as well as translate a vision to his team.
Henry Chao
Peter helped drive Intel's and Numonyx's NOR Flash development activities as the frontend integration team lead. In a very short time from when he joined the team, he was able to quickly absorb the complexities of the Flash process and take command of a focus team overseeing a large chunk of the process flow. A diligent and self-driven engineer, he helped identify new scaling techniques/architectures and resolved key frontend issues with minimal supervision, great discipline and detailed organization, all while maintaining excellent rapport with those he worked with. I found Peter to be a invaluable member of my team and strongly recommend him to any company looking for an excellent engineer able to quickly learn and drive critical activities.
Steven Soss
I had the pleasure of working with Peter to develop the 45nm self-aligned flash architecture for Intel and later Numonyx. During the time I worked with Peter, he was the front-end integration lead. Peter exhibited creativity as well as the ability to lead his integration team to meet the challenges of a new architecture. Though his leadership, the team developed several patentable scaling "tricks" and was able to stay within the existing capital equipment set to keep costs for the flash technology in line. I found Peter to be able to both motivate his team (process engineering and integration engineering) as well as work well with outside teams such as device, lithography, and product engineering teams. I can easily recommend Peter as someone who can innovate as well as translate a vision to his team.
Henry Chao
Peter helped drive Intel's and Numonyx's NOR Flash development activities as the frontend integration team lead. In a very short time from when he joined the team, he was able to quickly absorb the complexities of the Flash process and take command of a focus team overseeing a large chunk of the process flow. A diligent and self-driven engineer, he helped identify new scaling techniques/architectures and resolved key frontend issues with minimal supervision, great discipline and detailed organization, all while maintaining excellent rapport with those he worked with. I found Peter to be a invaluable member of my team and strongly recommend him to any company looking for an excellent engineer able to quickly learn and drive critical activities.
Steven Soss
I had the pleasure of working with Peter to develop the 45nm self-aligned flash architecture for Intel and later Numonyx. During the time I worked with Peter, he was the front-end integration lead. Peter exhibited creativity as well as the ability to lead his integration team to meet the challenges of a new architecture. Though his leadership, the team developed several patentable scaling "tricks" and was able to stay within the existing capital equipment set to keep costs for the flash technology in line. I found Peter to be able to both motivate his team (process engineering and integration engineering) as well as work well with outside teams such as device, lithography, and product engineering teams. I can easily recommend Peter as someone who can innovate as well as translate a vision to his team.
Experience
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Otsuka America, Inc.
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United States
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Pharmaceutical Manufacturing
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1 - 100 Employee
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Director of Engineering and Automation Systems
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Aug 2020 - Present
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Proteus Digital Health, Inc
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United States
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Pharmaceutical Manufacturing
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1 - 100 Employee
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Director of Process Integration
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2019 - Aug 2020
• Responsible for all change control related to Proteus’s Ingestible Sensor products• Oversee all Design Controls for Ingestible Sensor production and development• Liaison between engineering, operations, supply chain, and permissions departments and voice of customer
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Associate Director, Automation and Process Integration
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2015 - 2019
• Managed broad engineering teams (semiconductor, medical device, pharmaceutical, RF, automation, and contract manufacturers (CMOs)) to deliver a scalable and capable next generation ingestible sensor under 21 CFR 820 and ISO13485• Designed, developed, implemented, proceduralized, and deployed high-volume solutions for Digital Medicine manufacture• Interfaced with Quality Assurance, Regulatory Affairs, Clinical Affairs, and Pharmaceutical partners for Ingestible Sensor Design Controls and Regulatory submissions, including the world’s first Digital Medicine New Drug Application (NDA) with Otsuka’s MyCite Digital Abilify Show less
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Manager & Senior Manager, Semiconductor Process Engineering
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2011 - 2015
• Coordinated production and corrected issues as the lead operations interface to foundries, test house, subcontractors, and suppliers• Drove semiconductor engineering team in effort to increase production output while cutting manufacturing costs; achieved a 10 times increase in wafer output while simultaneously reducing cost 60%• Generated budgets and produced forecast based on customer demands for the semiconductor department
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Senior Staff Process Engineer
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2009 - 2011
• Developed scalable semiconductor process for a novel self-powered ingestible sensor resulting in an 80-times increase in functional device yield• Established SPC on the ingestion sensor semiconductor line, directly leading to a 4-times decrease in losses at metallization• Managed several NPI projects by coordinating cross disciplinary teams across the semiconductor, medical device, and pharmaceutical groups
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Numonyx
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Switzerland
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Semiconductor Manufacturing
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300 - 400 Employee
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Staff Process Architecture Integration Engineer
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2008 - 2009
• Global Technology Development Team Leader • Delivered 1 quarter pull-in of technology transfer to Israel site factory of 45nm NOR flash development line by setting technical milestones and success criteria that achieved process and yield matching on first silicon out • As Frontend Chair, interfaced with product designers to introduce process/lithography friendly layout changes, eliminating fundamental defect modes • Global Technology Development Team Leader • Delivered 1 quarter pull-in of technology transfer to Israel site factory of 45nm NOR flash development line by setting technical milestones and success criteria that achieved process and yield matching on first silicon out • As Frontend Chair, interfaced with product designers to introduce process/lithography friendly layout changes, eliminating fundamental defect modes
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Intel
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Semiconductor Manufacturing
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100 - 200 Employee
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Senior Process Integration Engineer
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2005 - 2008
• Chaired the Frontend Development team of the 45nm NOR flash technology through coordination of various teams, including process, device, yield, reliability, failure analysis and layout • Designed experiments (DOE) and spearheaded many task forces to develop and troubleshoot frontend technical issues, improve yield and meet reliability goals • Delivered Frontend Process in half the time of previous technology node • Hands-on involvement in every stage of development cycle, from path-finding to high volume manufacture Show less
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UC Davis
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United States
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Health, Wellness & Fitness
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1 - 100 Employee
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Post Doctoral Researcher
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2003 - 2005
• Developed photonic crystal patterning for integrated InP devices based on E-Beam Lithography and Focused Ion Beam etching • Fabricated of InP Arrayed Waveguide Gratings, Mach-Zehnder Interferometers and Mode-Locked Lasers; established InP back lapping and polishing procedure • Developed photonic crystal patterning for integrated InP devices based on E-Beam Lithography and Focused Ion Beam etching • Fabricated of InP Arrayed Waveguide Gratings, Mach-Zehnder Interferometers and Mode-Locked Lasers; established InP back lapping and polishing procedure
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Teaching Assistant
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1995 - 2002
• Head TA for Microfabrication (MOS and MEMS) and Device Physics• Defined and Designed Laboratory Projects for Students
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Engineering Research Assistant
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1995 - 2001
• Created Strained Channel SiGeC PMOS Devices with 20% Mobility Enhancement using a Novel Low Temperature Process Flow• Demonstrated MOS and Bipolar Functionality on Novel Low Temperature Bonded SOI Material• Semiconductor equipment superuser - responsible for recipe development and routine maintenance - designed, setup, and fabricated test equipment - repaired donated equipment in UC Davis microfabrication facility (Epitaxy, Diffusion/Oxidation, CVD, PVD, Lithography, Etch - Dry & Wet, Clean, Characterization) Show less
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C-Cube Microsystems
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Semiconductor Manufacturing
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100 - 200 Employee
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Engineering Summer Intern
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2000 - 2000
• Operated as a Microfabrication Foundry Liaison, coordinating 0.13 µm Design Rule specifications for multiple foundry compatibility • Simulated transistor performance (SPICE) for foundry cross qualification and compatibility • Operated as a Microfabrication Foundry Liaison, coordinating 0.13 µm Design Rule specifications for multiple foundry compatibility • Simulated transistor performance (SPICE) for foundry cross qualification and compatibility
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Lawrence Semiconductor Research Laboratories
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United States
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Veterinary
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Engineering Summer Intern
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1998 - 1998
• Epitaxially grew and characterized strained Group IV semiconductor layers and devices • Designed experiments (DOE) using JMP to explore physical & electrical properties response to composition, strain, and crystallinity • Epitaxially grew and characterized strained Group IV semiconductor layers and devices • Designed experiments (DOE) using JMP to explore physical & electrical properties response to composition, strain, and crystallinity
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Engineering CoOp
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1996 - 1998
• Process integration and failure analysis in development of High Voltage SOI product line • Linked electrical test anomalies to physical process phenomena and corrective action • Process integration and failure analysis in development of High Voltage SOI product line • Linked electrical test anomalies to physical process phenomena and corrective action
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Education
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University of California, Davis
Ph.D, Electrical Engineering -
University of California, Davis
M.S., Electrical Engineering -
University of California, Davis
Double B.S., Electrical Engineering and Materials Science
Community
