Experience

5 Systems

• Hungary
• Semiconductor Manufacturing
• 1 - 100 Employee

• Principal Design and Verification Engineer, Co-Founder

  • Jan 2021 - Present

  Specialised to support partners, who are building or planning to build power efficient systems Tailored verification approach fitting to project timelines, team expertise and available toolset Design and implemantation of tool agnostic design flows tailored to customer requirements Design and implement UVM verification components Review and optimize existing testbenches focusing on re-usablity and efficiency Specialised to support partners, who are building or planning to build power efficient systems Tailored verification approach fitting to project timelines, team expertise and available toolset Design and implemantation of tool agnostic design flows tailored to customer requirements Design and implement UVM verification components Review and optimize existing testbenches focusing on re-usablity and efficiency



AIStorm INC

• United States
• Semiconductor Manufacturing
• 1 - 100 Employee

• Principal Digital Design and Verification Engineer

  • Jun 2019 - Jan 2021

  Development of state of the art AI-In-Sensor solutions aiming high computation capacity with ultra low power consumption. Responsibilities: - Design of the architecture of the digital controller - Elaborate specifics and implement the design for multiple products - Create verification plans - Execute the verification - Implement verification components re-used across multiple projects - Optimize verification procedures - Modeling of the resource requirements of different AI structures



ARM

• United Kingdom
• Semiconductor Manufacturing
• 700 & Above Employee

• Staff Design and Verification engineer

  • Oct 2016 - Jun 2019

  Verification of subsystems integrating ARM CPUs targeting IoT markets. - Verification lead of IoT subsystems integrating M-Class CPUs, ARM security solution and CoreSight technology - Detailed verification planning and plan execution - UVM verification environment and test development - Formal verification - Bare metal C test development Verification of subsystems integrating ARM CPUs targeting IoT markets. - Verification lead of IoT subsystems integrating M-Class CPUs, ARM security solution and CoreSight technology - Detailed verification planning and plan execution - UVM verification environment and test development - Formal verification - Bare metal C test development



Imagination Technologies

• United Kingdom
• Semiconductor Manufacturing
• 700 & Above Employee

• Leading Verification Engineer

  • Jun 2014 - Aug 2016

  Verification of PowerVR Wizard family of graphics IP GPUs implementing Ray Tracing technology - Verification planning and execution - UVM verification of subsystems and standalone IPs - Highly configurable UVM verification component development to imitate multi-level cached memory hierarchy behaviour - Leading verification engineer of the Ray Tracing group - Analyse the power consumption of the SoC - Catch X propagation issues on RTL before synthesis - Unify regression environments of different module level verification environments - Make sure to provide compact release packages for the costumer



Duolog Technologies

• United Kingdom
• Software Development
• 1 - 100 Employee

• Verification Engineer

  • Oct 2012 - Jun 2014

  On-Site functional verification of an USB2.0 device and verification of the integration of the same IP to SoC.Responsibilities: - Create verification plan and strategy - Design verification environment on IP level - Implement use case scenarios - Reuse the verification environment and use cases on SoC level verificaton

• Verification Engineer

  • Apr 2012 - Oct 2012

  Services - BFM groupParticipated in the functional verification of several synthesizable BFMs.Responsibilities: - Cooperated in the requirement specification - Cooperated in creating verification plan and strategy - Designed the complete makefle driven design flow of the project by providing makefile templates and scripts to compile, elaborate the design, to run simulations, regressions, to evaluate the regression result and to merge coverage. - Designed highly configurable and reusable generic verification environment - Designed verification environment for the I2C BFM using the generic verification environment

• Verification Engineer

  • Jan 2009 - Apr 2012

  Services (TI IPP group)Participated in the development process of the OMAP family of Texas Intruments as verification engineer. Verified the USB 3.0 OTG module functionality on IP level and its integration on subsystem level.Responsibilities: - Cooperated in the verification plan and strategy elaboration - Developed the verification environment of the USB3.0 OTG IP in cooperation with two colleagues - Developed USB2.0 datapath test cases - Developed USB2.0 OTG test cases to cover scenarios using Session Request Protocol (SRP) and Host Negotiation Protocol (HNP) - Developed the Specman test bench of the subsystem level verification - Ported the USB2.0 specific test scenarios to the subsystem level verification - Provided support for the SoC level verification team - Verified the USB3.0 OTG IP integration to a system containing multiple USB2.0 Host, PCIe and USB3.0 OTG modules.



Budapest University of Technology and Economics

• Hungary
• Higher Education
• 700 & Above Employee

• Research associate

  • Jan 2008 - Jul 2008

  I took part in an interdisciplinary research along with a professor of electrical engineering and three neurologists. My goal was to grade the movement of people with neurological disorders to support the diagnostics of patients with Stroke or Parkinson’s disease. For analysis I have been using Matlab. IFMBE Proceedings, 2008, Volume 20, Part 3, 127-130, DOI: 10.1007/978-3-540-69367-3_34 Objective Evaluation of Stroke Patients’ Movement Ákos Jobbágy, P. Simon, G. Fazekas, P. Harcos and Z. Grosz