Peavy Hsu
Chief Engineer at VISHAY GENERAL SEMICONDUCTOR TAIWAN LTD.- Claim this Profile
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Bio
Experience
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VISHAY GENERAL SEMICONDUCTOR TAIWAN LTD.
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Taiwan
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Appliances, Electrical, and Electronics Manufacturing
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1 - 100 Employee
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Chief Engineer
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Jun 2020 - Present
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Chang Wah technology
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Taiwan
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R&D staff engineer
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Feb 2017 - Jun 2020
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Vishay Siliconix Inc
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Taiwan
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Research And Development Engineer
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Sep 2008 - Feb 2017
Project management -Package type : Power device / SOP8 / QFN / Flip chip -Simulation ANSYS and multi-physics Package structure simulation by ANSYS mechanical module Package electrical resistance simulation by ANSYS EMAG module Temperature cycling and thermal fatigue simulation with Visco-plastic model (Anand's model) Thermal analysis under Natural convection/ Force convection by ANSYS CFX module -Molding process Support sample build set-up in molding stage. Parameter fine tune New equipment/ New mold chase design New Compound evaluation -Lead-free project. Ag plated wafer with sintering die attach or solder Sliver Sintering material -Chemical deflash process Support sample build set-up in chemical deflash stage. Parameter fine tune -Solder flux cleaning process( machine/solvent) evaluation to improve W/B yield - High Density and big panel L/F design - Failure analysis for the defect products from customer or production line - Handling the raw material abnormality and feedback to raw material vendor - Flip clip device design and development . Show less
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walton advanced Engineering
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Semiconductors
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1 - 100 Employee
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Research and Development Engineer
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May 2006 - Sep 2008
Stage: Molding -Package type : CSP / Card device(ex. Micro SD )/SOP8 -New material evaluation and cost reduction. -New process or new device evaluation -High Density and big panel substrate design by 2 block mold cavity. -LED in card type Card type memory package(Patent :US 20090294792 A1) Stage: Molding -Package type : CSP / Card device(ex. Micro SD )/SOP8 -New material evaluation and cost reduction. -New process or new device evaluation -High Density and big panel substrate design by 2 block mold cavity. -LED in card type Card type memory package(Patent :US 20090294792 A1)
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ASE Global
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Taiwan
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Semiconductor Manufacturing
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700 & Above Employee
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Process Engineer
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Feb 2002 - Jan 2004
Stage: Molding Package type : PBGA / HSBGA -In charge of evaluation to replace non-green compound to green molding compound. -Process review and optimum and yield maintenance and improvement. -New material evaluation and cost reduction. -Defined and optimum molding parameter to improve warpage/coplanarity issue for PBGA package. -Handling and preparing the 8D or CAR report for customer complaints. Stage: Molding Package type : PBGA / HSBGA -In charge of evaluation to replace non-green compound to green molding compound. -Process review and optimum and yield maintenance and improvement. -New material evaluation and cost reduction. -Defined and optimum molding parameter to improve warpage/coplanarity issue for PBGA package. -Handling and preparing the 8D or CAR report for customer complaints.
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