Vice President, Hardware Security Products

• Aug 2023 - Present

Sr Staff Product Manager, Signal and Power Integrity EDA Software Solutions

• Dec 2021 - Apr 2023

Senior staff product management leader for Signal and Power Integrity Software EDA solutions - PrimeSim HSPICE SIPI Environment with focus on Memory and SerDes applications such as Datacenter, Memory, HPC Discover and validate market problems for Signal and Power Integrity Analyze customer segments and built business model(s) for new EDA software Bring new product concepts to life; build roadmaps; Promote at events - Signal and Power Integrity SIG 2023 and SIPI webpage Manage ERM/MRM/TRMs for top 28 customers of Synopsys Show less

Deputy Director, Product Marketing

• Nov 2019 - Nov 2021

Sales Enablement & Solutions Marketing Manager - Product Applications, Training & Global SE

• Mar 2019 - Jun 2019

Sales Enablement & Solutions Marketing Manager - Product Applications, Training and Global SE

• Apr 2018 - Mar 2019

 Work with product lines to identify products from the categories of Renesas’s MCU’s, IDT’s Clock/Timing products(Clock Generators, Buffers, Crystal Oscillators), Wireless Charging Power TXs and RXs, PMICs, Distributed Power Units(DPU), Pressure/Humidity/Temperature/Bio/Liquid/Gas sensors suitable for key applications such as Smart Phone/Tablet, Smart Home Appliances, Agricultural Drones, Car Infotainment system, HVAC, Smart Watch etc. Then created training collateral for Sales/FAEs to help cross sell and upsell IDT/Renesas products. Work involved developing application block diagrams by working with product engineers from across product lines at IDT/Renesas  Launched and managed weekly Sales/FAE product and application training program at IDT for 160+ sales at IDT and Onboarding training program for 400+ sales at Renesas, Organize Sales Training planning meetings with product lines to ensure quality in training offerings  Plan, schedule, manage and track Sales Training Calendar aligned with RTM, Campaign and Press releases.  Developed Sales Enablement Strategy, defined KPIs and roadmap; Conduct QBA and report SE program metrics to VP of Sales Show less

Project Lead, Contractor - Wireless Power Charging System Modeling & Simulation

• Jun 2017 - Dec 2017

 Schematic Simulator: SIMPLIS  Project Managed and Developed SIMPLIS system model for Samsung Wireless Power mobile system - 5W and 15W application with P9242 Wireless Charging Transmitter and P9221 Wireless Charging Receiver  Worked closely with Wireless Smart Phone Applications Manager to turn requirements into a simulation model  Schematic Simulator: SIMPLIS  Project Managed and Developed SIMPLIS system model for Samsung Wireless Power mobile system - 5W and 15W application with P9242 Wireless Charging Transmitter and P9221 Wireless Charging Receiver  Worked closely with Wireless Smart Phone Applications Manager to turn requirements into a simulation model

Project Lead/Manager – Online Design, Simulation and Analysis Platform Tools

• Jun 2008 - Apr 2017

 Develop backend JAVA based models for new RTM or older SMPS DC-DC ICs such as Buck, Boost, Inverting Buck Boost; AC-DC ICs such as Flyback Controller, PMUs and DDR LDO Terminators to integrated into WEBENCH. Work involves coding selection algorithms for BOM components (such as Transformer, MOSFET, Output Inductor, Output Capacitor, Diode etc) on the power supply board, code in equations that calculate power loss from key components on power supply design, compute efficiency of the board/system, and also code algorithms to perform control loop calculations, generate charts, operating values. Work also involves integrating TISPICE (converted from PSPICE) models into WEBENCH backend TISPICE simulator for each of the PMIC/PMU. All devices integrated into WEBENCH Power Designer are also utilized in WEBENCH Power Architect that offers multi-rail solutions to build system power tree per end consumer application, particularly one involving Memory, FPGAs and Microprocessors. Examples of my work: (Testing below product links requires myTI Login. Flash player needed for TPS65131 and LP2998)o Sync Buck Controller TPS40170; Integrated Buck Converter TPS53318 o AC-DC Quasi Resonant PWM Controller LM5023 o Power Management Unit (PMU) with Inverting Buck-Boost and Boost Channels TPS65131o DDR Power LP2998 Architected new features such as TISPICE based simulation capability, schematic export, simulation export in existing WEBENCH Power Designer and Power Architect. Improved library algorithms involving MOSFET power loss and efficiency calculation for Buck, Boost and Buck-Boost external FET Controller topologies for high Output Current spec (7A), resulting in an increase of customer’s Controller based designs by 63%, with number of designs created increase from 55000 to 90000 (tracked through Tableau) per quarter(MORE on RESUME) Show less

Lead – IBIS model generation

• Jun 2008 - Mar 2012

 Design: Cadence IC Design tool DF2, Cadence Allegro SIMULATORS: Cadence Spectre (Linux), Synopsys HSPICE Established concrete IBIS model generation methodology and trained 20+ engineers to develop IBIS and HSPICE models. Created, managed and improved modeling processes at TI. Built test bench templates in TISPICE3 and Cadence Spectre® to generate IBIS characteristics for CMOS, LVDS, PECL, CML, SATA PCIe Gen 1 / 2, USB v3.0, and USB v2.0 technologies. Used software tools to convert simulation data into IBIS format. Created IBIS modeling methodology documents for training purposes. Created IBIS Quality, IBIS vs. Spice Correlation standards and templates for both internal teams and sub-contractors. Held several IBIS training sessions for Analog eLab™ team members and external TI-contractors to bring consistency into IBIS modeling techniques. Identified gaps in modeling processes to reduce cycle time to generate quality IBIS models to meet pre-RTM release requirements. Created quality and pre-release requirements checklists, performed QA for peer and vendor generated models Show less

Electrical Modeling/Simulation Engineer

• Feb 2005 - Jun 2008

 Design: Cadence IC Design tool DF2, Cadence Allegro, Cadence Virtuoso for Layout  SIMULATORS: ModelSim 6.2d, HyperLynx Boardsim and LineSim, ELDO/ADMS Simulator, ICX 3.6 ISMB, HSPICE, Cadence SPB 16.0 – PCB SI, SigXP, Model Integrity, SiSoft – Quantum-SI  Developed analog simulation IC models in formats such as IBIS, encrypted HSPICE; Eldo SPICE, Package Simulation models, and memory DIMM simulation models to perform system level signal integrity, timing and cross talk analysis. Such simulation models were generated before the release of products such as Micron’s DRAM – DDR-I, II, III, IV, PSRAM and Flash memory.  Created power bus models for various memory components for use in SSO simulations and power integrity analysis.  Built IBIS-EBD (Electronic Board Description files) for memory modules such as UDIMM and RDIMM  Keeping track of release dates and follow strict schedule for model release that is tied to product RTM Show less