Papu Maharana

Design Engineer at MaxLinear
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Contact Information
us****@****om
(386) 825-5501
Location
Bengaluru, Karnataka, India, IN
Languages
  • English Limited working proficiency
  • Hindi Full professional proficiency
  • Odia Native or bilingual proficiency

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Credentials

  • Hardware Description Languages for FPGA Design
    Coursera
    Nov, 2020
    - Nov, 2024
  • Introduction to FPGA Design for Embedded Systems
    Coursera
    Nov, 2020
    - Nov, 2024
  • Python Classes and Inheritance
    Coursera
    Aug, 2020
    - Nov, 2024
  • Python Functions, Files, and Dictionaries
    Coursera
    Aug, 2020
    - Nov, 2024
  • Data Collection and Processing with Python
    Coursera
    Aug, 2020
    - Nov, 2024
  • Python Basics
    Coursera
    Jul, 2020
    - Nov, 2024
  • RISC-V RV32I RTL Design using Verilog HDL
    Maven Silicon
    Jan, 2021
    - Nov, 2024
  • VLSI System On Chip Design
    Maven Silicon
    Mar, 2021
    - Nov, 2024
  • VLSI Verification
    Maven Silicon
    Jan, 2021
    - Nov, 2024
  • Programming with C and C++
    Internshala
    Sep, 2020
    - Nov, 2024

Experience

  • MaxLinear
    • United States
    • Semiconductor Manufacturing
    • 700 & Above Employee
    • Design Engineer
      • Feb 2023 - Present

  • FrenusTech Pvt Ltd
    • India
    • Semiconductor Manufacturing
    • 1 - 100 Employee
    • Design Engineer
      • Jul 2020 - Jan 2023

      > Working Experience in Lint | CDC | Logic Synthesis | SDCs | STA | Joules | GLS. > Designed I2C | AXI | APB | JTAG | UART_16550 Protocols. > Good Knowledge in RISCV ISA | RISCV CSRs. > Designed RISCV32I Processor. > Worked on Design Change & Debugging of RISCV CSRs Block. > Working Experience in Lint | CDC | Logic Synthesis | SDCs | STA | Joules | GLS. > Designed I2C | AXI | APB | JTAG | UART_16550 Protocols. > Good Knowledge in RISCV ISA | RISCV CSRs. > Designed RISCV32I Processor. > Worked on Design Change & Debugging of RISCV CSRs Block.

  • Electronics Corporation of India Limited (ECIL), Department of Atomic Energy, Government of India.
    • India
    • Defense & Space
    • 500 - 600 Employee
    • VLSI Design Training
      • May 2018 - Jun 2018

      In this training, 1. I have learned Verilog hardware description language and design digital circuits using Xilinx software. 2. Worked on the project FPGA implementation of Digital Code Lock using Verilog HDL. In this training, 1. I have learned Verilog hardware description language and design digital circuits using Xilinx software. 2. Worked on the project FPGA implementation of Digital Code Lock using Verilog HDL.

Education

  • Veer Surendra Sai University Of Technology ( Formerly UCE ), Burla
    BTech - Bachelor of Technology, Electronics and Communications Engineering
    2016 - 2020
  • Science College, Hinjilicut
    intermediate, Science
    2012 - 2014

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