Experience

Alphachip

• Appliances, Electrical, and Electronics Manufacturing
• 1 - 100 Employee

• Senior Staff Engineer/ Full time Contractor (ON Semiconductor)

  • Jan 2009 - Present

  Memory Compiler verification. Verilog and VHDL behavioral, Fastscan and Tetramax DFT, Logic Vision models creation/modification. Functional verification, SDF back annotation (NC-tools, Questasim, VCS). Memory Compiler verification. Verilog and VHDL behavioral, Fastscan and Tetramax DFT, Logic Vision models creation/modification. Functional verification, SDF back annotation (NC-tools, Questasim, VCS).



Microstyle, Moscow, Russia

• Senior Staff Engineer/ Full time Contractor (Motorola SPS/Freescale)

  • Apr 2002 - Dec 2008

  Memory Compiler verification. Team leader since May 2005. Plan, coordinate and supervise efforts of Functional Verification group of 3 engineers. Activities include design specification review/modifications, test plan, test suit, regression tests, working with designers on issues; memory behavioral model creation/modifications, code coverage evaluation with Cadence ICCR, SDF back annotation check, Fastscan model and ATPG patterns creation. Memory Compiler verification. Team leader since May 2005. Plan, coordinate and supervise efforts of Functional Verification group of 3 engineers. Activities include design specification review/modifications, test plan, test suit, regression tests, working with designers on issues; memory behavioral model creation/modifications, code coverage evaluation with Cadence ICCR, SDF back annotation check, Fastscan model and ATPG patterns creation.



IPPM, Russian Academy of Science, Moscow, Russia

• Senior Engineer/ Full Time Contractor (Motorola SPS)

  • Aug 1997 - Mar 2002

  Memory Compilers Design and Characterization.

• Senior Engineer/ Full Time Contractor (Motorola ECO)

  • Jun 1993 - Aug 1997

  Digital Signal Array processor architecture implementation in Motorola's H4C standard cell library.VeComP701 16-bit SIMD Processor Project. Design/synthesis and functional verification of Synchronous Serial Interface (SSI).



Scientific-Production Center "ELVIS-AP", Moscow, Russia

• Design Engineer

  • Mar 1991 - May 1993

  Digital Array Signal Processor, Synthetic Aperture Radar Vision (SAR). Logic design and verification. Digital Array Signal Processor, Synthetic Aperture Radar Vision (SAR). Logic design and verification.



NII Microdevices, Moscow, Russia

• Design engineer

  • May 1989 - Feb 1991

  Digital Array Signal Processor, Synthetic Aperture Radar Vision (SAR). Logic design and verification. Digital Array Signal Processor, Synthetic Aperture Radar Vision (SAR). Logic design and verification.