Experience

Sventl Asia Pacific

• Singapore
• Semiconductors
• 1 - 100 Employee

• Sr. ATE Test Engineer

  • Jul 2023 - Present



onsemi

• United States
• Semiconductors
• 700 & Above Employee

• ATE Test Engineer 2 (Post Silicon Validation)

  • Aug 2020 - Jun 2023

  1) 2+ Years of experience with ON Semiconductor (Onsemi) in Test and Characterization of Re-Driver devices at wafer/package level using Teradyne Microflex ATE tester. 2) Feasibility study for project/device to tester resource. 3) Test Plan development based on the data sheet test parameters and device functionality. 4) Hardware design (Schematic Development + Layout File review) for DUT based on available tester resource & DUT test specification. 5) Initial board checks by using multimeter before and after component assembly. 6) Developing Test Programs and debugging by using Test Development / Debug Environment (TDE), Oscilloscope and Multimeter. 7) Characterization of ReDriver devices across Temperatures and Voltages. 8) Test Program & Hardware qualification – Hardware GRR, Intersite GRR, Repeatability check, Spike, CPK analysis, Test Time. 9) ATE Report preparation and presentation. 10) Test Program release to production. 11) Test time optimization and Yield improvements activities. Show less



Tessolve

• India
• Semiconductor Manufacturing
• 700 & Above Employee

• ATE Test Engineer 2 (Post Silicon Validation)

  • Jul 2017 - Jul 2020

  Advantest 93K - SMT 7 / SMT 8 1) Test plan for all IO pads and High-Speed IO blocks. 2) Load board & Probe card schematics review. 3) Pre-Si checks to make sure proper vector delivery. 4) Test program development for High-Speed IO blocks and DC parameters, Validation by using 93K tester. 5) Test program debug by using Timing Diagram, Shmoo and Error map. 6) Involved in High-Speed IO blocks USB2.0, USB3.0, PCIe2.0 and PCIe3.0 vectors debug for functionality, Vmin and Shmoo analysis across PVT. 7) Involved in Internal Loopback, External Loopback, Sigdet, TxRx-Detect and Tx-DC levels patterns bring up for USB3 and PCIe blocks. 8) Involved in LS/FS/HS speed BIST tests, HS/FS Rx DC input and HS/FS Tx DC output measurements bring up for USB2.0 block. 9) Involved in DC vectors debug for functionality & verification of DC parameters like VIL/VIH, VOL/VOH, Leakage, Pull-Up, Pull-Down tests. 10) Char Program bring up, Char Report preparation and presentation. 11) Involved in multisite program preparation and validation. 12) Version control: SVN, GIT. 13) Issues Tracker: Jira 14) Involved in various test time saving activities. Show less