Experience

Uniquify Inc

• United States
• Semiconductor Manufacturing
• 1 - 100 Employee

• Senior Analog Design Engineer

  • Jul 2014 - Present

  - Experiences on DDR IO high-speed interface, low-power interface in 7nm/12nm/22nm/28nm/40nm/55nm/65nm CMOS & FinFet (Transmitter/Receiver/Calibration/Amplifier/Level Shifter/Biasing current source/Voltage reference/PLL/ESD) - Design Delay Line linearity step resolution smaller 3ps with dutycycle variation <1% . - Design IO analog blocks/Function verification/Characterization & timing verification/Optimization performance, areas & power, building testbench for simulate multiple blocks connection, create verification plans. - SI/PI simulation using IO Netlist/IBIS/PCB/PKG/RDL/PDN models - EMIR verification & Layout optimization. - SPICE simulation, DC, AC, Transient, Monte Carlo, S parameters, noise analysis, Aging force. - Generation full DDR IO cells & standard cells LIB. - Experiences on Cadence/Synopsys/Cliosoft tools such as Hspice/Spectre/NanoSpice/VCS MATLAB/Virtuoso/Star-RC/XRC/Ultrasim/Voltus Fi. - Perl/TCL/Cshell scripting language. - Dashboard report for data analysis, writing technical specification documents. Show less



eSilicon

• United States
• Semiconductor Manufacturing
• 100 - 200 Employee

• Intership

  • Nov 2013 - Jun 2014