Yashas Nagavane Dattatreya

uArch and RTL Design engineer at Rivos Inc.
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Contact Information
us****@****om
(386) 825-5501
Location
Mountain View, California, United States, US

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Credentials

  • Learning FPGA Development
    LinkedIn
    Jan, 2022
    - Nov, 2024
  • LFD103: A Beginner's Guide to Linux Kernel Development
    The Linux Foundation
    Feb, 2021
    - Nov, 2024

Experience

    • United States
    • Computer Hardware Manufacturing
    • 100 - 200 Employee
    • uArch and RTL Design engineer
      • Jun 2023 - Present

    • United States
    • Semiconductor Manufacturing
    • 700 & Above Employee
    • Intern
      • Jan 2023 - May 2023

    • United States
    • Higher Education
    • 700 & Above Employee
    • On campus roles
      • Jan 2022 - May 2023

      • Mentor - CSCI 356 - Introduction to Computer Systems - Appointed by Prof. Marco Paolieri (Fall 2022) • Grader - EE 457 - Computer Systems Organization - Appointed by Prof. Gandhi Puvvada (Spring 2022) • Student Technical Assistant - USC Information Technology Services. (Fall 2021 - Spring 2023) • Mentor - CSCI 356 - Introduction to Computer Systems - Appointed by Prof. Marco Paolieri (Fall 2022) • Grader - EE 457 - Computer Systems Organization - Appointed by Prof. Gandhi Puvvada (Spring 2022) • Student Technical Assistant - USC Information Technology Services. (Fall 2021 - Spring 2023)

    • United States
    • Software Development
    • 700 & Above Employee
    • Hardware Engineering Intern
      • May 2022 - Aug 2022

    • India
    • Software Development
    • 1 - 100 Employee
    • RTL Design Engineer (Junior Research Fellow)
      • Aug 2020 - Jun 2021

      Project 1:• Wrote RTL for a 64 × 64 cached matrix-multiplication accelerator on Intel Stratix 10 FPGA.• Designed recursive high-speed full-cycle LFSRs for use in caching FIFOs.• Interfaced multiplier AFU with Intel CCI-P (Core Cache Interface). This achieves state-of-the-art throughput of 2.5 TFLOPS at 309MHz.Project 2:Cluster monitoring and controlling tool.Supports:• Unified graphical view of cluster machines• User login activities• Remote reboot/shutdown support• RAM and CPU usage monitoring Show less

    • Digital Logic Design Intern
      • Feb 2018 - Aug 2020

      • Wrote RTL for a 16 × 16 matrix-multiplication accelerator on Intel Arria 10, CPU+FPGA platform.• Improved FMAX by 60% from 250MHz to 400MHz over initial implementation Resulting in a peak of 204.8 GFLOPSThis was awarded the "Best Poster Presentation" award at the 2020 VLSID conference.

    • India
    • Semiconductor Manufacturing
    • 1 - 100 Employee
    • Student Intern
      • Jan 2020 - Jun 2020

      Worked on multiple applications powered by various ML architectures such as GANs, CNNs. Worked on application development for BUDDHI Kit, India's first AI-DIY Kit. Worked on multiple applications powered by various ML architectures such as GANs, CNNs. Worked on application development for BUDDHI Kit, India's first AI-DIY Kit.

    • India
    • Higher Education
    • 500 - 600 Employee
    • Teaching Assistant
      • Aug 2019 - Dec 2019

      • Worked as a TA for the course "Digital Design and Computer Organization". • Assistance during the lab sessions. • Worked as a TA for the course "Digital Design and Computer Organization". • Assistance during the lab sessions.

    • Higher Education
    • 700 & Above Employee
    • Summer Intern
      • Jun 2019 - Aug 2019

      Investigated image-related, and audio-related ML techniques using GANs, CNNs, and RNNs. Introduction and using frameworks such as TensorFlow, PyTorch, and Apache MXNet. Investigated image-related, and audio-related ML techniques using GANs, CNNs, and RNNs. Introduction and using frameworks such as TensorFlow, PyTorch, and Apache MXNet.

Education

  • University of Southern California
    Master's degree, Computer Engineering
    2021 - 2023
  • PES University
    B.Tech, Computer Science and Engineering
    2016 - 2020
  • Manasarovar Pushkarini Vidyashram PU College (Deeksha integrated)
    Pre University, Computer Science, Mathematics, Physics, and Chemistry
    2014 - 2016
  • Mahajana Public School
    10th, 10/10 CGPA
    2011 - 2014
  • Kendriya Vidyalaya
    2004 - 2011

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