Yashas Nagavane Dattatreya
uArch and RTL Design engineer at Rivos Inc.- Claim this Profile
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Bio
Credentials
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Learning FPGA Development
LinkedInJan, 2022- Nov, 2024 -
LFD103: A Beginner's Guide to Linux Kernel Development
The Linux FoundationFeb, 2021- Nov, 2024
Experience
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Rivos Inc.
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United States
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Computer Hardware Manufacturing
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100 - 200 Employee
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uArch and RTL Design engineer
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Jun 2023 - Present
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AMD
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United States
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Semiconductor Manufacturing
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700 & Above Employee
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Intern
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Jan 2023 - May 2023
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University of Southern California
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United States
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Higher Education
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700 & Above Employee
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On campus roles
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Jan 2022 - May 2023
• Mentor - CSCI 356 - Introduction to Computer Systems - Appointed by Prof. Marco Paolieri (Fall 2022) • Grader - EE 457 - Computer Systems Organization - Appointed by Prof. Gandhi Puvvada (Spring 2022) • Student Technical Assistant - USC Information Technology Services. (Fall 2021 - Spring 2023) • Mentor - CSCI 356 - Introduction to Computer Systems - Appointed by Prof. Marco Paolieri (Fall 2022) • Grader - EE 457 - Computer Systems Organization - Appointed by Prof. Gandhi Puvvada (Spring 2022) • Student Technical Assistant - USC Information Technology Services. (Fall 2021 - Spring 2023)
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Google
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United States
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Software Development
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700 & Above Employee
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Hardware Engineering Intern
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May 2022 - Aug 2022
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Center for Cloud Computing and Big Data, PES University
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India
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Software Development
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1 - 100 Employee
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RTL Design Engineer (Junior Research Fellow)
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Aug 2020 - Jun 2021
Project 1:• Wrote RTL for a 64 × 64 cached matrix-multiplication accelerator on Intel Stratix 10 FPGA.• Designed recursive high-speed full-cycle LFSRs for use in caching FIFOs.• Interfaced multiplier AFU with Intel CCI-P (Core Cache Interface). This achieves state-of-the-art throughput of 2.5 TFLOPS at 309MHz.Project 2:Cluster monitoring and controlling tool.Supports:• Unified graphical view of cluster machines• User login activities• Remote reboot/shutdown support• RAM and CPU usage monitoring Show less
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Digital Logic Design Intern
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Feb 2018 - Aug 2020
• Wrote RTL for a 16 × 16 matrix-multiplication accelerator on Intel Arria 10, CPU+FPGA platform.• Improved FMAX by 60% from 250MHz to 400MHz over initial implementation Resulting in a peak of 204.8 GFLOPSThis was awarded the "Best Poster Presentation" award at the 2020 VLSID conference.
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CYRAN AI Solutions
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India
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Semiconductor Manufacturing
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1 - 100 Employee
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Student Intern
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Jan 2020 - Jun 2020
Worked on multiple applications powered by various ML architectures such as GANs, CNNs. Worked on application development for BUDDHI Kit, India's first AI-DIY Kit. Worked on multiple applications powered by various ML architectures such as GANs, CNNs. Worked on application development for BUDDHI Kit, India's first AI-DIY Kit.
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PES University
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India
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Higher Education
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500 - 600 Employee
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Teaching Assistant
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Aug 2019 - Dec 2019
• Worked as a TA for the course "Digital Design and Computer Organization". • Assistance during the lab sessions. • Worked as a TA for the course "Digital Design and Computer Organization". • Assistance during the lab sessions.
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Indian Institute of Technology, Delhi
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Higher Education
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700 & Above Employee
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Summer Intern
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Jun 2019 - Aug 2019
Investigated image-related, and audio-related ML techniques using GANs, CNNs, and RNNs. Introduction and using frameworks such as TensorFlow, PyTorch, and Apache MXNet. Investigated image-related, and audio-related ML techniques using GANs, CNNs, and RNNs. Introduction and using frameworks such as TensorFlow, PyTorch, and Apache MXNet.
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Education
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University of Southern California
Master's degree, Computer Engineering -
PES University
B.Tech, Computer Science and Engineering -
Manasarovar Pushkarini Vidyashram PU College (Deeksha integrated)
Pre University, Computer Science, Mathematics, Physics, and Chemistry -
Mahajana Public School
10th, 10/10 CGPA -
Kendriya Vidyalaya