Experience

MediaTek

• Taiwan
• Semiconductor Manufacturing
• 700 & Above Employee

• Technical Manager

  • Jun 2021 - Present

• Staff Engineer

  • Jun 2017 - May 2021

• Senior Physical Design Engineer

  • Jul 2014 - May 2017



Wipro

• India
• IT Services and IT Consulting
• 700 & Above Employee

• Physical Design Engineer

  • Aug 2011 - Jul 2014

  knowledge on Complete Full-Custom/Semi-Custom ASIC Design flow at Deep Submicron Level.Complete Physical Design flow involving Design Planning, Floorplanning, Powerplanning, Place & Route, Clock Tree Synthesis, Timing Analysis and Closure, Physical Verification.Knowledge of Static Timing Analysis. Hands on experience on using Synopsys Prime-Time.Hands on Experience on Industry Standard EDA Tools from Synopsys and Cadence. knowledge on Complete Full-Custom/Semi-Custom ASIC Design flow at Deep Submicron Level.Complete Physical Design flow involving Design Planning, Floorplanning, Powerplanning, Place & Route, Clock Tree Synthesis, Timing Analysis and Closure, Physical Verification.Knowledge of Static Timing Analysis. Hands on experience on using Synopsys Prime-Time.Hands on Experience on Industry Standard EDA Tools from Synopsys and Cadence.