Experience

Athena Cloud Engineers, LLC

• United States
• Design
• 1 - 100 Employee

• Principal ASIC Physical Design Engineer Consultant

  • Mar 2019 - Present

  Over 40 years of engineering experience. Mantra: customer is number one and deliver quality work. Consulting on ASIC designs from synthesis through tape out to Foundries. Companies worked at: IBM, Cadence, Synopsys, Apple, Broadcom, SIEMENS, Infineon, GOOGLE, startups and more. I have completed work from the start to tape-out. My work included 5nm process and foundries like IBM, Global Foundries, INTEL, Samsung to name a few. Eda tools: Genus, Tempus, ICC2, Design Compiler, Innovus, Calibre… Show more Over 40 years of engineering experience. Mantra: customer is number one and deliver quality work. Consulting on ASIC designs from synthesis through tape out to Foundries. Companies worked at: IBM, Cadence, Synopsys, Apple, Broadcom, SIEMENS, Infineon, GOOGLE, startups and more. I have completed work from the start to tape-out. My work included 5nm process and foundries like IBM, Global Foundries, INTEL, Samsung to name a few. Eda tools: Genus, Tempus, ICC2, Design Compiler, Innovus, Calibre, StarRCXT, Voltus, RedHawk, etc. To widen my breadth of experience, I have also been involved in a startup, sales, and business development. I also have included mentoring other engineers, without obligation. Email to office@athenacloudengineers.com Show less Over 40 years of engineering experience. Mantra: customer is number one and deliver quality work. Consulting on ASIC designs from synthesis through tape out to Foundries. Companies worked at: IBM, Cadence, Synopsys, Apple, Broadcom, SIEMENS, Infineon, GOOGLE, startups and more. I have completed work from the start to tape-out. My work included 5nm process and foundries like IBM, Global Foundries, INTEL, Samsung to name a few. Eda tools: Genus, Tempus, ICC2, Design Compiler, Innovus, Calibre… Show more Over 40 years of engineering experience. Mantra: customer is number one and deliver quality work. Consulting on ASIC designs from synthesis through tape out to Foundries. Companies worked at: IBM, Cadence, Synopsys, Apple, Broadcom, SIEMENS, Infineon, GOOGLE, startups and more. I have completed work from the start to tape-out. My work included 5nm process and foundries like IBM, Global Foundries, INTEL, Samsung to name a few. Eda tools: Genus, Tempus, ICC2, Design Compiler, Innovus, Calibre, StarRCXT, Voltus, RedHawk, etc. To widen my breadth of experience, I have also been involved in a startup, sales, and business development. I also have included mentoring other engineers, without obligation. Email to office@athenacloudengineers.com Show less


Self-employed
• Real Estate
• 1 - 100 Employee
• Principal Consultant

  • May 2018 - Present


Mobiveil Inc.

• United States
• Semiconductor Manufacturing
• 200 - 300 Employee

• ASIC Physical Design Engineer

  • Mar 2019 - Mar 2019

  Consulting at ASTERA LABS,INC. Sunnyvale, California • Tools: ICC2, ICV, VUE, Sed/AWK, TcL, Makefile • Process: TSMC **CONFIDENTIAL *** • Std Cell Library: TSMC • Completed work: Urgent, right before tapeout, DRC, LVS, ANT verification, repair Consulting at ASTERA LABS,INC. Sunnyvale, California • Tools: ICC2, ICV, VUE, Sed/AWK, TcL, Makefile • Process: TSMC **CONFIDENTIAL *** • Std Cell Library: TSMC • Completed work: Urgent, right before tapeout, DRC, LVS, ANT verification, repair



Intel Corporation

• United States
• Semiconductor Manufacturing
• 700 & Above Employee

• Design Automation Engineer consultant

  • Apr 2017 - May 2018

  Continue working at Intel Corp. at Santa Clara as an employee of Esencia Technologies, Inc. The work includes programming in Tcl to do full chip integration. Using ICC2 in the process on the hierarchical full chip integration. Using Perforce for versioning control. Developing scripts to allow for full chip intergration. Using 10nm INTEL ASIC and custom libraries. All work is being done at the top level. The work includes doing DRC checking using SYNOPSYS icv and icwbev. I cannot discuss the… Show more Continue working at Intel Corp. at Santa Clara as an employee of Esencia Technologies, Inc. The work includes programming in Tcl to do full chip integration. Using ICC2 in the process on the hierarchical full chip integration. Using Perforce for versioning control. Developing scripts to allow for full chip intergration. Using 10nm INTEL ASIC and custom libraries. All work is being done at the top level. The work includes doing DRC checking using SYNOPSYS icv and icwbev. I cannot discuss the detail, but all is very exciting. Show less Continue working at Intel Corp. at Santa Clara as an employee of Esencia Technologies, Inc. The work includes programming in Tcl to do full chip integration. Using ICC2 in the process on the hierarchical full chip integration. Using Perforce for versioning control. Developing scripts to allow for full chip intergration. Using 10nm INTEL ASIC and custom libraries. All work is being done at the top level. The work includes doing DRC checking using SYNOPSYS icv and icwbev. I cannot discuss the… Show more Continue working at Intel Corp. at Santa Clara as an employee of Esencia Technologies, Inc. The work includes programming in Tcl to do full chip integration. Using ICC2 in the process on the hierarchical full chip integration. Using Perforce for versioning control. Developing scripts to allow for full chip intergration. Using 10nm INTEL ASIC and custom libraries. All work is being done at the top level. The work includes doing DRC checking using SYNOPSYS icv and icwbev. I cannot discuss the detail, but all is very exciting. Show less

• ASIC Senior Physical Design Engineer Consultant

  • Aug 2016 - Feb 2017

  Hired to consult on-site for Intelliswift as a Senior Physical Designer. This included 10nm technology, place and route, using INTEL design flow, EDA tools by Synopsys (for example ICC2), project management and floorplanning exploration and timing convergence and deliver a floorplan that includes 4 large each 2 million gates blocks. Project also included, documentation of tasks, status reports and meetings. Hired to consult on-site for Intelliswift as a Senior Physical Designer. This included 10nm technology, place and route, using INTEL design flow, EDA tools by Synopsys (for example ICC2), project management and floorplanning exploration and timing convergence and deliver a floorplan that includes 4 large each 2 million gates blocks. Project also included, documentation of tasks, status reports and meetings.



Qualcomm

• United States
• Telecommunications
• 700 & Above Employee

• ASIC Physical Designer Consultant

  • Jun 2016 - Aug 2016

  Contracted to do synthesis/floorplanning/place and route/cts/static timing analysis/extraction/LVS/DRC/DFM. Challenge, to improve performance of a taped out design. Technology is 180nm and EDA tools are Cadence/Synopsys/Mentor Graphics. Contracted to do synthesis/floorplanning/place and route/cts/static timing analysis/extraction/LVS/DRC/DFM. Challenge, to improve performance of a taped out design. Technology is 180nm and EDA tools are Cadence/Synopsys/Mentor Graphics.



Eximius Design

• United States
• IT Services and IT Consulting
• 200 - 300 Employee

• Senior ASIC Physical Design Engineer Consultant

  • Feb 2016 - May 2016

  Contracted to take a soft IP and harden it by taking the synthesized netlist through place and route and qualifying it using timing reports and physical verification. Automated the design and tools flow by scripting the environment. The EDA tools are Cadence Innovus and the technology is TSMC 16nm using the Avago 16nm standard cell library. The harden IP is over 20 million gates. Contracted to take a soft IP and harden it by taking the synthesized netlist through place and route and qualifying it using timing reports and physical verification. Automated the design and tools flow by scripting the environment. The EDA tools are Cadence Innovus and the technology is TSMC 16nm using the Avago 16nm standard cell library. The harden IP is over 20 million gates.



Broadcom

• United States
• Semiconductor Manufacturing
• 700 & Above Employee

• ASIC Physical Designer (consultant)

  • Nov 2015 - Jan 2016

  Contracted to do full chip static timing analsys and physical design. Deliverables are scripts to help analyze timing relation issues and solutions to timing violations. I worked with other timing engineers to help converge on timing at the full chip. Analyzed timing reports from Cadence Tempes and Place and route scripts from ATOP Technologies. Contracted to do full chip static timing analsys and physical design. Deliverables are scripts to help analyze timing relation issues and solutions to timing violations. I worked with other timing engineers to help converge on timing at the full chip. Analyzed timing reports from Cadence Tempes and Place and route scripts from ATOP Technologies.



PNY Technologies

• United States
• Computers and Electronics Manufacturing
• 200 - 300 Employee

• Technical Marketing Engineer Consultant

  • Oct 2014 - Sep 2015

  Write technical collaterals: datasheets, app notes, white papers, product briefs, technical product training materials to help train sales and marketing team and establish quicker adoption of PNY SSD products. Work with content experts to define gaps in existing content, and develop appropriate content solutions addressing the needs. Work with cross functional teams to characterize PNY SSD, performance benchmark and generate collateral to help competitive positioning of the product and to… Show more Write technical collaterals: datasheets, app notes, white papers, product briefs, technical product training materials to help train sales and marketing team and establish quicker adoption of PNY SSD products. Work with content experts to define gaps in existing content, and develop appropriate content solutions addressing the needs. Work with cross functional teams to characterize PNY SSD, performance benchmark and generate collateral to help competitive positioning of the product and to communicate the value. Manage and help drive third party reviews and validations of competitive technical data including at application and synthetic test level. Support Marketing and Business Development efforts to broaden the customer base, support design win-design-in opportunities. Develop demos, proof points etc. for roadshows to establish product goodness and showcase user perceivable value additions. Lead discussion panels at conferences and industry group events and/or product shows. Show less Write technical collaterals: datasheets, app notes, white papers, product briefs, technical product training materials to help train sales and marketing team and establish quicker adoption of PNY SSD products. Work with content experts to define gaps in existing content, and develop appropriate content solutions addressing the needs. Work with cross functional teams to characterize PNY SSD, performance benchmark and generate collateral to help competitive positioning of the product and to… Show more Write technical collaterals: datasheets, app notes, white papers, product briefs, technical product training materials to help train sales and marketing team and establish quicker adoption of PNY SSD products. Work with content experts to define gaps in existing content, and develop appropriate content solutions addressing the needs. Work with cross functional teams to characterize PNY SSD, performance benchmark and generate collateral to help competitive positioning of the product and to communicate the value. Manage and help drive third party reviews and validations of competitive technical data including at application and synthetic test level. Support Marketing and Business Development efforts to broaden the customer base, support design win-design-in opportunities. Develop demos, proof points etc. for roadshows to establish product goodness and showcase user perceivable value additions. Lead discussion panels at conferences and industry group events and/or product shows. Show less



AMD

• France
• Architecture and Planning
• 1 - 100 Employee

• MTS (Member of Technical Staff) Design Engineer

  • Apr 2013 - Jun 2014

  • Technical member of the SERDES1 IP design team. • Using process down to 20nm. • Using Synopsys ICC & Primetime, Mentor Graphics Calibre, and Cadence SOC Encounter. • Using advance design automation internal tools. Also, using Perforce and FlowTracer for design automation. • Application of circuit design or logic optimization to converge on timing. • Responsible for physical design implementation of complex SoCs. • Participating in physical design methodologies and flow… Show more • Technical member of the SERDES1 IP design team. • Using process down to 20nm. • Using Synopsys ICC & Primetime, Mentor Graphics Calibre, and Cadence SOC Encounter. • Using advance design automation internal tools. Also, using Perforce and FlowTracer for design automation. • Application of circuit design or logic optimization to converge on timing. • Responsible for physical design implementation of complex SoCs. • Participating in physical design methodologies and flow automation. • Floorplan, place&route, signal integrity avoidance/fixing, power/clock distribution, timing closure - timing, power, clock and noise analysis and DRC/LVS.Timing closure. clock/power distribution & analysis, signal integrity, and DFM. • Writing scripts in SED, AWK, Python, Tcl and Perl.

• ASIC Physical Design Engineer Consultant

  • Sep 2011 - Apr 2013

  Using Synopsys ICC & Primetime, Mentor Graphics Calibre, and Cadence SOC Encounter. Using advance design automation internal tools. Also, using Perforce and FlowTracer for design automation. Using process down to 28nm. Application of circuit design or logic optimization to converge on timing. Responsible for physical design implementation of complex SoCs. Participating in physical design methodologies and flow automation. Floorplan, place&route, signal integrity avoidance/fixing, power/clock… Show more Using Synopsys ICC & Primetime, Mentor Graphics Calibre, and Cadence SOC Encounter. Using advance design automation internal tools. Also, using Perforce and FlowTracer for design automation. Using process down to 28nm. Application of circuit design or logic optimization to converge on timing. Responsible for physical design implementation of complex SoCs. Participating in physical design methodologies and flow automation. Floorplan, place&route, signal integrity avoidance/fixing, power/clock distribution, timing closure - timing, power, clock and noise analysis and DRC/LVS.Timing closure. clock/power distribution & analysis, signal integrity, and DFM. Writing scripts in SED, AWK, Tcl and Perl.



Synapse Design Automation Inc.

• Senior Physical Desgn Engineer Consultant

  • Jun 2011 - Jul 2011

  Using Synopsys ICC & Primetime, MAGMA Talus, Mentor Graphics Calibre, and Cadence SOC Encounter. Using process down to 40nm. Responsible for physical design implementation of complex SoCs. Participating in physical design methodologies and flow automation. Floorplan, place&route, signal integrity avoidance/fixing, power/clock distribution, timing closure - timing, power, clock and noise analysis and DRC/LVS.Timing closure. clock/power distribution & analysis, signal integrity, and DFM. Writing… Show more Using Synopsys ICC & Primetime, MAGMA Talus, Mentor Graphics Calibre, and Cadence SOC Encounter. Using process down to 40nm. Responsible for physical design implementation of complex SoCs. Participating in physical design methodologies and flow automation. Floorplan, place&route, signal integrity avoidance/fixing, power/clock distribution, timing closure - timing, power, clock and noise analysis and DRC/LVS.Timing closure. clock/power distribution & analysis, signal integrity, and DFM. Writing scripts in SED, AWK, Tcl and Perl. Show less Using Synopsys ICC & Primetime, MAGMA Talus, Mentor Graphics Calibre, and Cadence SOC Encounter. Using process down to 40nm. Responsible for physical design implementation of complex SoCs. Participating in physical design methodologies and flow automation. Floorplan, place&route, signal integrity avoidance/fixing, power/clock distribution, timing closure - timing, power, clock and noise analysis and DRC/LVS.Timing closure. clock/power distribution & analysis, signal integrity, and DFM. Writing… Show more Using Synopsys ICC & Primetime, MAGMA Talus, Mentor Graphics Calibre, and Cadence SOC Encounter. Using process down to 40nm. Responsible for physical design implementation of complex SoCs. Participating in physical design methodologies and flow automation. Floorplan, place&route, signal integrity avoidance/fixing, power/clock distribution, timing closure - timing, power, clock and noise analysis and DRC/LVS.Timing closure. clock/power distribution & analysis, signal integrity, and DFM. Writing scripts in SED, AWK, Tcl and Perl. Show less



ChipStart

• Italy
• Restaurants
• 1 - 100 Employee

• Business Manager Consultant

  • Mar 2011 - Apr 2011

  Responsible for identifying, qualifying and closing IP sales opportunities for ChipStart, LLC in Northern California (Silicon Valley). Achieve revenue targets. Manage relationships at management & operational levels with customers and partners. Sales forecasting with high degree of accuracy. Understand customer needs/expectations and decision making process. Identify and qualify projects. Build accurate pipeline to manage priorities and provide forecast. Define account plans and execute them… Show more Responsible for identifying, qualifying and closing IP sales opportunities for ChipStart, LLC in Northern California (Silicon Valley). Achieve revenue targets. Manage relationships at management & operational levels with customers and partners. Sales forecasting with high degree of accuracy. Understand customer needs/expectations and decision making process. Identify and qualify projects. Build accurate pipeline to manage priorities and provide forecast. Define account plans and execute them through effective planning of resources. Present proposals, manage negotiations and close the sales. Gain strategic information about customers and the industry to help anticipate market trends. Participation in trade shows, client conferences, industry events, etc. Partner with and develop key relationships with Regional head (management), Business Team (product marketing, product specialist), and Professional Services (pre and post sales support). Build and leverage relationships with existing and potential customers and partners. Use of CRM tools. Track and provide feedback on quality of leads. Show less Responsible for identifying, qualifying and closing IP sales opportunities for ChipStart, LLC in Northern California (Silicon Valley). Achieve revenue targets. Manage relationships at management & operational levels with customers and partners. Sales forecasting with high degree of accuracy. Understand customer needs/expectations and decision making process. Identify and qualify projects. Build accurate pipeline to manage priorities and provide forecast. Define account plans and execute them… Show more Responsible for identifying, qualifying and closing IP sales opportunities for ChipStart, LLC in Northern California (Silicon Valley). Achieve revenue targets. Manage relationships at management & operational levels with customers and partners. Sales forecasting with high degree of accuracy. Understand customer needs/expectations and decision making process. Identify and qualify projects. Build accurate pipeline to manage priorities and provide forecast. Define account plans and execute them through effective planning of resources. Present proposals, manage negotiations and close the sales. Gain strategic information about customers and the industry to help anticipate market trends. Participation in trade shows, client conferences, industry events, etc. Partner with and develop key relationships with Regional head (management), Business Team (product marketing, product specialist), and Professional Services (pre and post sales support). Build and leverage relationships with existing and potential customers and partners. Use of CRM tools. Track and provide feedback on quality of leads. Show less



Ruben Reyes

• United States
• Construction

• Engineering/Sales/Business Development Consultant

  • Feb 2011 - Mar 2011

  Strategic Consulting, including business plan & sales strategy development. Strategic Consulting, including business plan & sales strategy development.



Trivium Tech Force Corporation

• Principal Engineer and Founder

  • Feb 2010 - Jan 2011

  • Responsible for the development of strategic account penetration plans and annual bookings objectives for IP products. • Responsible for developing business proposals and negotiating large value opportunities define and maintain detailed account development plan for IP and design services based opportunities. These plans should include sales goals, strategic target goals and plans to grow partner’s commitment. • Included weekly reports on account progress, develop and own strategic and… Show more • Responsible for the development of strategic account penetration plans and annual bookings objectives for IP products. • Responsible for developing business proposals and negotiating large value opportunities define and maintain detailed account development plan for IP and design services based opportunities. These plans should include sales goals, strategic target goals and plans to grow partner’s commitment. • Included weekly reports on account progress, develop and own strategic and tactical relationships at management, engineering and marketing levels; gain understanding of informal decision making organization. • Work with sales team to negotiate and close contracts for IP based products. • Represent partner to customer and provide feedback to design partners, engineering, marketing and management regarding partner technical and business requirements. • Facilitate contract deliverables to partners and manage issues that arise Identify and capture competitive landscape, trends, unit and ASP projections, acquisition activities and other relevant partner information. • Gain working knowledge of partner technical and business strengths, target markets Show less • Responsible for the development of strategic account penetration plans and annual bookings objectives for IP products. • Responsible for developing business proposals and negotiating large value opportunities define and maintain detailed account development plan for IP and design services based opportunities. These plans should include sales goals, strategic target goals and plans to grow partner’s commitment. • Included weekly reports on account progress, develop and own strategic and… Show more • Responsible for the development of strategic account penetration plans and annual bookings objectives for IP products. • Responsible for developing business proposals and negotiating large value opportunities define and maintain detailed account development plan for IP and design services based opportunities. These plans should include sales goals, strategic target goals and plans to grow partner’s commitment. • Included weekly reports on account progress, develop and own strategic and tactical relationships at management, engineering and marketing levels; gain understanding of informal decision making organization. • Work with sales team to negotiate and close contracts for IP based products. • Represent partner to customer and provide feedback to design partners, engineering, marketing and management regarding partner technical and business requirements. • Facilitate contract deliverables to partners and manage issues that arise Identify and capture competitive landscape, trends, unit and ASP projections, acquisition activities and other relevant partner information. • Gain working knowledge of partner technical and business strengths, target markets Show less



Global Trivium Corporation

• Semiconductors

• Principal Engineer and Founder

  • Mar 2009 - Feb 2010

  • Responsible for the development of strategic account penetration plans and annual bookings objectives for IP products. • Responsible for developing business proposals and negotiating large value opportunities define and maintain detailed account development plan for IP and design services based opportunities. These plans should include sales goals, strategic target goals and plans to grow partner’s commitment. • Included weekly reports on account progress, develop and own strategic and… Show more • Responsible for the development of strategic account penetration plans and annual bookings objectives for IP products. • Responsible for developing business proposals and negotiating large value opportunities define and maintain detailed account development plan for IP and design services based opportunities. These plans should include sales goals, strategic target goals and plans to grow partner’s commitment. • Included weekly reports on account progress, develop and own strategic and tactical relationships at management, engineering and marketing levels; gain understanding of informal decision making organization. • Work with sales team to negotiate and close contracts for IP based products. • Represent partner to customer and provide feedback to design partners, engineering, marketing and management regarding partner technical and business requirements. • Facilitate contract deliverables to partners and manage issues that arise Identify and capture competitive landscape, trends, unit and ASP projections, acquisition activities and other relevant partner information. • Gain working knowledge of partner technical and business strengths, target markets Show less • Responsible for the development of strategic account penetration plans and annual bookings objectives for IP products. • Responsible for developing business proposals and negotiating large value opportunities define and maintain detailed account development plan for IP and design services based opportunities. These plans should include sales goals, strategic target goals and plans to grow partner’s commitment. • Included weekly reports on account progress, develop and own strategic and… Show more • Responsible for the development of strategic account penetration plans and annual bookings objectives for IP products. • Responsible for developing business proposals and negotiating large value opportunities define and maintain detailed account development plan for IP and design services based opportunities. These plans should include sales goals, strategic target goals and plans to grow partner’s commitment. • Included weekly reports on account progress, develop and own strategic and tactical relationships at management, engineering and marketing levels; gain understanding of informal decision making organization. • Work with sales team to negotiate and close contracts for IP based products. • Represent partner to customer and provide feedback to design partners, engineering, marketing and management regarding partner technical and business requirements. • Facilitate contract deliverables to partners and manage issues that arise Identify and capture competitive landscape, trends, unit and ASP projections, acquisition activities and other relevant partner information. • Gain working knowledge of partner technical and business strengths, target markets Show less

• IC Physical Design Engineer & Project Management Consultant

  • Jul 2008 - Mar 2009

  Recommended and experience is developing designs flows from synthesis to tape-out GDS in Synopsys, Cadence and MAGMA using 65nm process nodes and higher. Including the proven ability to manage projects, interview, qualify and hire design engineers. Recommended and experience is developing designs flows from synthesis to tape-out GDS in Synopsys, Cadence and MAGMA using 65nm process nodes and higher. Including the proven ability to manage projects, interview, qualify and hire design engineers.



QThink

• United States
• Information Technology & Services

• Senior Design Engineer

  • Oct 2004 - Jul 2008

  * ASIC Physical Design from netlist to GDSII. * ASIC Design Methodology Development. * Tools flow development and evaluation. * Worked with Sales in new development deals for new business opportunities. * Developed brand strategies with Sales. * Strategic Consulting, including business plan & sales strategy development for start-ups. * ASIC Physical Design from netlist to GDSII. * ASIC Design Methodology Development. * Tools flow development and evaluation. * Worked with Sales in new development deals for new business opportunities. * Developed brand strategies with Sales. * Strategic Consulting, including business plan & sales strategy development for start-ups.



Synopsys

• Staff Corporate Applicaton Engineer

  • Sep 1998 - Dec 2003

  Support customers using Astro/Physical Compiler/other backend tools from Synopsys Support R&D in tool testing and developement Support Coprorate Application Engineers. Develop test plans Develop product features Develop tools flows and design methodologies Support customers using Astro/Physical Compiler/other backend tools from Synopsys Support R&D in tool testing and developement Support Coprorate Application Engineers. Develop test plans Develop product features Develop tools flows and design methodologies



Cadence Design Systems

• United States
• Software Development
• 700 & Above Employee

• Senior Design Consultant

  • Feb 1993 - Oct 1998

  Physical design using Cadence Virtuoso, CELL3, Preview, taped out designs using Silicon Ensemble, LEF&DEF, SED&AWK scripting, Floorplanning, Place&Route, using 0.35um process, design methodology development and assessment, EDA support for Silicon Ensemble and DRACULA. Physical design using Cadence Virtuoso, CELL3, Preview, taped out designs using Silicon Ensemble, LEF&DEF, SED&AWK scripting, Floorplanning, Place&Route, using 0.35um process, design methodology development and assessment, EDA support for Silicon Ensemble and DRACULA.



IBM Thomas J. Watson Research Center

• Engineer

  • Dec 1982 - Jan 1993

  * Touch screen research & product development. * Worked on IBM's leading edge submicron technology in custom physical design & methodology. * Worked on several IBM chips and products: PowerPC 630 chip, TouchSelect, 4055 Infowindows, 8516 Touchscreen, and the Advanced Technology Classrooms, & systems on a chip(ASIC). * Worked with IBM's leading edge submicron technology (cmos5x and cmos7) in custom physical design. As well as setting up a design methodology for measuring performance… Show more * Touch screen research & product development. * Worked on IBM's leading edge submicron technology in custom physical design & methodology. * Worked on several IBM chips and products: PowerPC 630 chip, TouchSelect, 4055 Infowindows, 8516 Touchscreen, and the Advanced Technology Classrooms, & systems on a chip(ASIC). * Worked with IBM's leading edge submicron technology (cmos5x and cmos7) in custom physical design. As well as setting up a design methodology for measuring performance when doing custom physical design. * Designed a custom 64-bit register, using IBM technology, hard block for a CPU chip for the datapath. Using cmos5x, 0.25micron IBM technology. Physical design and verification (IBM Niagara and Cadence Dracula). * Created and lead in establishing one way of doing remote verification for his custom physical design team. * I took an intensive CMOS design course by IBM and instructors from Columbia, Cornell, and MIT. * Co-authored several IBM white papers. Show less * Touch screen research & product development. * Worked on IBM's leading edge submicron technology in custom physical design & methodology. * Worked on several IBM chips and products: PowerPC 630 chip, TouchSelect, 4055 Infowindows, 8516 Touchscreen, and the Advanced Technology Classrooms, & systems on a chip(ASIC). * Worked with IBM's leading edge submicron technology (cmos5x and cmos7) in custom physical design. As well as setting up a design methodology for measuring performance… Show more * Touch screen research & product development. * Worked on IBM's leading edge submicron technology in custom physical design & methodology. * Worked on several IBM chips and products: PowerPC 630 chip, TouchSelect, 4055 Infowindows, 8516 Touchscreen, and the Advanced Technology Classrooms, & systems on a chip(ASIC). * Worked with IBM's leading edge submicron technology (cmos5x and cmos7) in custom physical design. As well as setting up a design methodology for measuring performance when doing custom physical design. * Designed a custom 64-bit register, using IBM technology, hard block for a CPU chip for the datapath. Using cmos5x, 0.25micron IBM technology. Physical design and verification (IBM Niagara and Cadence Dracula). * Created and lead in establishing one way of doing remote verification for his custom physical design team. * I took an intensive CMOS design course by IBM and instructors from Columbia, Cornell, and MIT. * Co-authored several IBM white papers. Show less