Experience

Global Engineering Services

• Pakistan
• IT Services and IT Consulting
• 1 - 100 Employee

• Senior FPGA Engineer

  • Sep 2015 - Present

  I'm working as a lead FPGA Engineer/Manager. My job responsibilities range from interacting with customers, documentation, technical team lead, design, development & verification. Following are some of the details.• Design & Development of RTL for a Xilinx Zynq Based Board used for an Ultrasound application. The design involved interfacing with LVDS, data movement from LVDS interface to USB interface using DMA. The design also involved configuration of chip via SPI. The Processing system was used for Data logging and configuration of RTL via memory mapped registers.• Design, Development, Verification and Hardware Validation of a USB3.0 Physical interface tester using Xilinx ZC706 board and a 3rd Party USB3.0 Host/Device• Design and Development of a 25Gx4 and 10Gx10 Ethernet tester• Design, Development and Verification of test suites for Hardware validation of FPGA based boards having high speed interfaces, Memory interface and Processing systems.• Development of Verification environment of FPGA based digital designs including the Processing systems• Development of next generation high speed serial bus designs• Project management activities• Developing project plans, interacting with customer and implementation as per schedule



Epic Technologies (Pvt) Ltd

• Computer Hardware Manufacturing

• Co Founder/CTO

  • May 2010 - Sep 2015

  • Design and Development of a 16 Layer board which does Image stitching on run time. The details of the board are as followingo Xilinx Virtex 6 FPGAo DDR3 interface with FPGAo Serial Interface to communicate with Beagle Boardo Six Camera Link Interfaces • Design and Development of Video Processing Board which does JPEG-2000 compression. The details of the board are as followingo Eight layer board with Spartan 3 FPGAo 16MB SDRAMo Analog Devices IC AD212 for JPEG compressiono Analog Device IC AD 7189 –Multi format SDTV Video Decodero Video Interface, USB Interface, Serial Port • Design and Development of an FPGA based Data Acquisition board. The details of the board are as followingo Four layer board with Spartan 2 FPGAo High-speed differential interface IL-422 transceivero 64 bit buffered data bus for interfacing with external card



Silicon Technology Solutions

• Semiconductor Manufacturing

• System Architect

  • Mar 2013 - Aug 2015

  • Lead a team of 4 engineers in the Verification of an FPGA based Network Packetizer/Depacketizer in VMM• Design, development & Verification of an FPGA based PCIe DMA Design • Lead a team of 4 engineers in the Verification of an FPGA based Network Packetizer/Depacketizer in VMM• Design, development & Verification of an FPGA based PCIe DMA Design



Open-Silicon, Inc.

• India
• Semiconductor Manufacturing
• 1 - 100 Employee

• System Architect

  • Apr 2012 - Apr 2013

  • Lead a team of 5 engineers in the Design, Development and Verification of DDR2/DDR3/DDR4 memory controller• Architected the Design of DDR2/DDR3/DDR4 memory controller• Implemented the RTL of DDR2/DDR3/DDR4 memory controller in Verilog• Designed the Verification environment of DDR2/DDR3/DDR4 memory controller in System Verilog and UVM• Tested the DDR3 Memory controller on Xilinx Virtex 6 FPGA at 666 MHz with Micron 512MB DDR3 DIMM.• Experience in integrating the DDR2/DDR3/DDR4 memory controller with different PHYs through the DFI interface.



Industrial IoT Security | Palmchip

• United States
• Technology, Information and Internet
• 1 - 100 Employee

• Associate System Architect

  • Sep 2011 - Mar 2012

  • Designed a SATA host model for verification purposes in System Verilog, based SATA 3.0 specifications• 128 bit AES implementation. • Designed a SATA host model for verification purposes in System Verilog, based SATA 3.0 specifications• 128 bit AES implementation.



Industrial IoT Security | Palmchip

• United States
• Technology, Information and Internet
• 1 - 100 Employee

• Principal Design Engineer/Sr. Design Engineer

  • Mar 2006 - Apr 2010

  • Design, Development and Verification of a FLASH controller for use in a SSD. A programmable FLASH controller, which could support all kinds of FLASH devices, asynchronous, synchronous, double data rate. • Design, Development and Verification of LZW compression/decompression algorithm. • Team Lead for the Design and Support of a Universal Flash Device Model, which supports over 200 devices from various vendors like Micron, Samsung, Toshiba, Sandisk. • Involved in the Verification of a Chip for Solid State Disk Drive • Design, Development and Verification of an AHB to MBus Bridge for USB 2.0 Host/Device controller. • Involved in the Design and Verification of DDR2 memory controller.



And Or Logic Pvt. Ltd.

• Computer Networking Products
• 1 - 100 Employee

• Design Engineer

  • Oct 2003 - Feb 2006

  • Design & Development of Transaction Translator of a USB 2.0 IF compliant Hub including design flow, RTL, test bench formation and debugging for customer (Atmel Corporation, San Jose, CA). • Design, Development and Verification 128 bit AES Encryption/Decryption Algorithm on Spartan 3 FPGA. • Design, Development and Verification of an 8 Layer PCI board with Spartan 3 FPGA and TI Processor. • Design, Development and Verification an 8 layer FPGA based USB 2.0 Analyzer board • Design & Development of Transaction Translator of a USB 2.0 IF compliant Hub including design flow, RTL, test bench formation and debugging for customer (Atmel Corporation, San Jose, CA). • Design, Development and Verification 128 bit AES Encryption/Decryption Algorithm on Spartan 3 FPGA. • Design, Development and Verification of an 8 Layer PCI board with Spartan 3 FPGA and TI Processor. • Design, Development and Verification an 8 layer FPGA based USB 2.0 Analyzer board