Experience

MICAS (KU Leuven)

• Belgium
• Research Services
• 1 - 100 Employee

• PHD Researcher

  • Oct 2018 - Present

  Leuven, Belgium ⋄ Study and characterization of thin-film devices for circuit design ⋄ Exploration of new and old circuit techniques for design without complementary active devices for circuit building blocks: amplifiers, comparators, logic topologies, memory etc. ⋄ Demonstrator circuits/systems for applications requiring large-area electronics: fully integrated flexible imagers, biomedical interface circuits ⋄ Comparison of competing thin-film technologies: Unipolar-IGZO vs CMOS-LTPS ⋄… Show more ⋄ Study and characterization of thin-film devices for circuit design ⋄ Exploration of new and old circuit techniques for design without complementary active devices for circuit building blocks: amplifiers, comparators, logic topologies, memory etc. ⋄ Demonstrator circuits/systems for applications requiring large-area electronics: fully integrated flexible imagers, biomedical interface circuits ⋄ Comparison of competing thin-film technologies: Unipolar-IGZO vs CMOS-LTPS ⋄ Applying the design techniques to other unipolar devices such as GaN-FET ⋄ Tapeout expeience with IGZO, LTPS and GaN-IC technologies Google Scholar https://scholar.google.com/citations?user=99TQUz8AAAAJ&hl=en Show less



imec

• Belgium
• Research Services
• 700 & Above Employee

• Masters Thesis Student

  • Sep 2017 - Jun 2018

  Leuven - Feasibility study of dataflow only architectures to perform 3D convolution in the context of convolutional neural networks (CNN) with custom beyond CMOS mixed signal building blocks -Mapping (3+1)D convolution to 2D pipelined data flow -Creation of a framework/architecture simulator for the design exploration to yield design options/tradeoffs -Proposal of feasible and efficient architectural solution



Cadence Design Systems

• United States
• Software Development
• 700 & Above Employee

• Design Engineer

  • Apr 2013 - Aug 2015

  Pune Design of custom instruction subset to accelerate specific functionality using Tensilica TIE HDL, with software kernels for testing. Characterization of design (TIE) + software kernels (C with intrinsics) via RTL/gate level power estimation using Cadence tool flow



Tensilica

• United States
• Semiconductor Manufacturing
• 1 - 100 Employee

• DSP design Engineer

  • Jul 2011 - Mar 2013

  Pune Area, India Implementation and software testing of SIMD+VLIW datapath extensions of the Xtensa processors for baseband signal processing algorithms, development of optimized software kernel libraries for basic signal processing routines. Optimization targeted to achieve maximum performance through software pipelining, SIMD aware algorithm transformations, data memory mapping.



National Instruments India

• Intern, DSP Engineering Group

  • May 2009 - Jul 2009

  Bangalore Created a LabView module to implement Jakes model for multipath fading. The module was tested as a part of a GPS signal generation software chain (transmitter simulator) with standard GPS receiver chip.