Experience

Sankalp Semiconductor
• United States
• Semiconductor Manufacturing
• 300 - 400 Employee
• Senior Layout Designer

  • May 2018 - Present


Zia Semiconductor Pvt Ltd

• India
• Semiconductor Manufacturing
• 1 - 100 Employee

• • Jun 2012 - Present

  SPHD SRAM: Leaf cell development and verification of top levelI/O layout including floor planning.Sense amplifier layout taking care of various critical parameters.I/O Latches, Mux and driver layoutLVS, DRC and abutment checks of I/OControl block optimization to reduce load and routing on critical signals.Top Level Checks, DRC, LVS etc.Boundary and Antenna Checks etc.DPSRAM: Leaf cell development and verification of top levelRow decoder layout and pitch matching Row decoder LVS/DRC and abutment DRCsI/O layoutLVS, DRC and abutment checks of I/OTop Level Checks, DRC, LVS etc.Boundary and Antenna Checks etc.11RF Register File Instance Development 512 x 64 mux 4 with maskComplete I/O floor plan, layout of various I/O modulesSense Amplifier layout with consideration of all critical sense parametersI/O LVS/DRC and abutment checksCustom Bitcell Layout Development considering all critical bitcell parametersHS RF 40nm Compiler DevelopmentDecoder LayoutVia programming and Decoder LVSTop Level DRC/LVSInstance level checksBoundary, antenna, diode checksHD SRAM Compiler Tweaking in 130nmTweaking of Control BlockInternal Clock Generator layout and simulationsDRC, LVS and Abutment checks and DFMAntenna checks, Diode checks and other top level checks Show less

• • Jun 2012 - Present

  SPHD SRAM: Leaf cell development and verification of top levelI/O layout including floor planning.Sense amplifier layout taking care of various critical parameters.I/O Latches, Mux and driver layoutLVS, DRC and abutment checks of I/OControl block optimization to reduce load and routing on critical signals.Top Level Checks, DRC, LVS etc.Boundary and Antenna Checks etc.DPSRAM: Leaf cell development and verification of top levelRow decoder layout and pitch matching Row decoder LVS/DRC and abutment DRCsI/O layoutLVS, DRC and abutment checks of I/OTop Level Checks, DRC, LVS etc.Boundary and Antenna Checks etc.11RF Register File Instance Development 512 x 64 mux 4 with maskComplete I/O floor plan, layout of various I/O modulesSense Amplifier layout with consideration of all critical sense parametersI/O LVS/DRC and abutment checksCustom Bitcell Layout Development considering all critical bitcell parametersHS RF 40nm Compiler DevelopmentDecoder LayoutVia programming and Decoder LVSTop Level DRC/LVSInstance level checksBoundary, antenna, diode checksHD SRAM Compiler Tweaking in 130nmTweaking of Control BlockInternal Clock Generator layout and simulationsDRC, LVS and Abutment checks and DFMAntenna checks, Diode checks and other top level checks Show less