Experience

Analog Bits

• United States
• Semiconductor Manufacturing
• 1 - 100 Employee

• Sr. Principal IC Design Engineer

  • Jun 2018 - Present

  Circuit and system designer of multi-Gbps SerDes receivers Circuit and system designer of multi-Gbps SerDes receivers



Amirkabir University of Technology - Tehran Polytechnic

• Iran
• Higher Education
• 700 & Above Employee

• Associate Professor

  • Feb 2014 - Present

  Faculty member and the director of Biomedical Circuits and Systems Lab. Faculty member and the director of Biomedical Circuits and Systems Lab.



Rambus

• United States
• Semiconductors
• 500 - 600 Employee

• Sr. Principal IC Design Engineer

  • Jun 2015 - Sep 2017

  Worked on defining the architecture of a 112Gbps multi-protocol SerDes PHY. Worked on defining the architecture of a 112Gbps multi-protocol SerDes PHY.



Synopsys Inc

• United States
• Software Development
• 700 & Above Employee

• Sr. II Analog IC Design Engineer

  • 2010 - 2014

  Designed high-speed analog circuits for multi-gigabit per second SerDes IPs in nanometer (down to 16nm) bulk, SOI and Finfet CMOS technologies: * Designed an LC-VCO-based PLL for a 16-GB/s multi-standard PHY IP in a 16nm Finfet process. * Guided the efforts for the generation of the IBIS AMI models for an advanced 1-10.3 GB/s SerDes IP. * Designed the CTLE and DFE blocks of a 1-10.3 GB/s SerDes receiver in a 28-nm CMOS process. * Was responsible for all aspects of clock… Show more Designed high-speed analog circuits for multi-gigabit per second SerDes IPs in nanometer (down to 16nm) bulk, SOI and Finfet CMOS technologies: * Designed an LC-VCO-based PLL for a 16-GB/s multi-standard PHY IP in a 16nm Finfet process. * Guided the efforts for the generation of the IBIS AMI models for an advanced 1-10.3 GB/s SerDes IP. * Designed the CTLE and DFE blocks of a 1-10.3 GB/s SerDes receiver in a 28-nm CMOS process. * Was responsible for all aspects of clock distribution and multiphase clock generation for a DFE Receiver dedicated to a 1-12.5 GB/s multi-standard PHY IP in a 28-nm CMOS process. This included the design of two DLLs and a Phase-Interpolator. * Designed multiple DACs and a precision auto-zero comparator for a 10.3 Gbps DFE receiver. * Designed the AFE block of SerDes receiver for a 1-6.4 GB/s PHY IP supporting multiple standards, in a 32nm CMOS SOI process. * Participated in the design of a voltage-mode transmitter for a 2.5-8 GB/s SerDes PHY IP supporting multiple standards, in a 45nm CMOS SOI process. Responsible for designing a DCC circuit, budgeting the TX launch amplitude, and designing the TX regulators. * Designed various LDO voltage regulators with high PSRRs and ultra-fast load regulations in multiple projects. * Successfully led a team of six CAD engineers and interns porting schematics and test-benches of a multi-protocol SerDes PHY IP from Cosmos (Synopsys’ old analog design environment) to Custom Designer (Synopsys’ present analog design environment). Show less Designed high-speed analog circuits for multi-gigabit per second SerDes IPs in nanometer (down to 16nm) bulk, SOI and Finfet CMOS technologies: * Designed an LC-VCO-based PLL for a 16-GB/s multi-standard PHY IP in a 16nm Finfet process. * Guided the efforts for the generation of the IBIS AMI models for an advanced 1-10.3 GB/s SerDes IP. * Designed the CTLE and DFE blocks of a 1-10.3 GB/s SerDes receiver in a 28-nm CMOS process. * Was responsible for all aspects of clock… Show more Designed high-speed analog circuits for multi-gigabit per second SerDes IPs in nanometer (down to 16nm) bulk, SOI and Finfet CMOS technologies: * Designed an LC-VCO-based PLL for a 16-GB/s multi-standard PHY IP in a 16nm Finfet process. * Guided the efforts for the generation of the IBIS AMI models for an advanced 1-10.3 GB/s SerDes IP. * Designed the CTLE and DFE blocks of a 1-10.3 GB/s SerDes receiver in a 28-nm CMOS process. * Was responsible for all aspects of clock distribution and multiphase clock generation for a DFE Receiver dedicated to a 1-12.5 GB/s multi-standard PHY IP in a 28-nm CMOS process. This included the design of two DLLs and a Phase-Interpolator. * Designed multiple DACs and a precision auto-zero comparator for a 10.3 Gbps DFE receiver. * Designed the AFE block of SerDes receiver for a 1-6.4 GB/s PHY IP supporting multiple standards, in a 32nm CMOS SOI process. * Participated in the design of a voltage-mode transmitter for a 2.5-8 GB/s SerDes PHY IP supporting multiple standards, in a 45nm CMOS SOI process. Responsible for designing a DCC circuit, budgeting the TX launch amplitude, and designing the TX regulators. * Designed various LDO voltage regulators with high PSRRs and ultra-fast load regulations in multiple projects. * Successfully led a team of six CAD engineers and interns porting schematics and test-benches of a multi-protocol SerDes PHY IP from Cosmos (Synopsys’ old analog design environment) to Custom Designer (Synopsys’ present analog design environment). Show less



onsemi

• United States
• Semiconductors
• 700 & Above Employee

• Sr. Analog IC Design Engineer / Project Leader

  • 2007 - 2010

  Designed analog and mixed-signal circuits for audio and biomedical applications. · Successfully led Sound Design Technologies’ first major product for a multi-billion dollar company targeted for non-hearing aid market. · Part of the team that designed the world’s first full system-on-chip for hearing aid applications (the chip, called Wolverine, is being mass-produced in the TSMC 90nm CMOS technology). The chip won the 2010 EDN Innovation award in the category of… Show more Designed analog and mixed-signal circuits for audio and biomedical applications. · Successfully led Sound Design Technologies’ first major product for a multi-billion dollar company targeted for non-hearing aid market. · Part of the team that designed the world’s first full system-on-chip for hearing aid applications (the chip, called Wolverine, is being mass-produced in the TSMC 90nm CMOS technology). The chip won the 2010 EDN Innovation award in the category of Multiprocessing. · Designed an ultra low-power (1 µW) and low-voltage (0.9 V), 9-bit 32-kS/s successive approximation ADC and performed its AMS simulation; this design was 500 times faster than its predecessor while consuming only one-fifth of the power. · Designed an H-Bridge class D power amplifier driven with an audio delta-sigma PDM DAC. · Designed a voltage doubler for EPROM read/write. · Participated in the design of the multi-power domain IO ring of the Wolverine chip. · Designed, implemented (using TI’s TMS320C6711 DSK board) and characterized an audio 5th-order 1.5-bit delta-sigma DAC. This design had 15dB better dynamic range than its predecessor while consuming only one-fourth of the power. · Designed an ultra low power, low jitter and low tempco CMOS ring oscillator, which had 14dB lower phase noise, and six times lower tempco while consuming the same power as its predecessor. · Designed and simulated an audio multibit delta-sigma PWM DAC with pre-distortion. · Investigated the effects of nonlinearity and clock jitter on the noise and dynamic range of an audio delta-sigma PDM DACs. · Designed and simulated a low-power and low voltage PLL frequency synthesizer. Show less Designed analog and mixed-signal circuits for audio and biomedical applications. · Successfully led Sound Design Technologies’ first major product for a multi-billion dollar company targeted for non-hearing aid market. · Part of the team that designed the world’s first full system-on-chip for hearing aid applications (the chip, called Wolverine, is being mass-produced in the TSMC 90nm CMOS technology). The chip won the 2010 EDN Innovation award in the category of… Show more Designed analog and mixed-signal circuits for audio and biomedical applications. · Successfully led Sound Design Technologies’ first major product for a multi-billion dollar company targeted for non-hearing aid market. · Part of the team that designed the world’s first full system-on-chip for hearing aid applications (the chip, called Wolverine, is being mass-produced in the TSMC 90nm CMOS technology). The chip won the 2010 EDN Innovation award in the category of Multiprocessing. · Designed an ultra low-power (1 µW) and low-voltage (0.9 V), 9-bit 32-kS/s successive approximation ADC and performed its AMS simulation; this design was 500 times faster than its predecessor while consuming only one-fifth of the power. · Designed an H-Bridge class D power amplifier driven with an audio delta-sigma PDM DAC. · Designed a voltage doubler for EPROM read/write. · Participated in the design of the multi-power domain IO ring of the Wolverine chip. · Designed, implemented (using TI’s TMS320C6711 DSK board) and characterized an audio 5th-order 1.5-bit delta-sigma DAC. This design had 15dB better dynamic range than its predecessor while consuming only one-fourth of the power. · Designed an ultra low power, low jitter and low tempco CMOS ring oscillator, which had 14dB lower phase noise, and six times lower tempco while consuming the same power as its predecessor. · Designed and simulated an audio multibit delta-sigma PWM DAC with pre-distortion. · Investigated the effects of nonlinearity and clock jitter on the noise and dynamic range of an audio delta-sigma PDM DACs. · Designed and simulated a low-power and low voltage PLL frequency synthesizer. Show less