Experience

Empower Semiconductor

• United States
• Semiconductor Manufacturing
• 1 - 100 Employee

• Staff Analog design engineer

  • Sep 2020 - Present

  Multi phase DC-DC Buck converter: -clock/PLL, -Phase Extrapolator, -Delta-Sigma current monitor, -RC network, ... Multi phase DC-DC Buck converter: -clock/PLL, -Phase Extrapolator, -Delta-Sigma current monitor, -RC network, ...



PsiQuantum

• United States
• Computer Hardware Manufacturing
• 100 - 200 Employee

• Senior Analog/Mixed signal engineer

  • Jan 2020 - Sep 2020

  -Modeling new and existing blocks in Verilog/Veriloga: High speed MUX’es, Bias generators, Current steering DAC, Current mirrors, Analog test bus -Designed, supervised layout and verified a couple different High speed 4X 256:1 MUX’es in 22nm FDX GF, for selecting the appropriate signal from Single Photon Detector -Designed, characterized and verified layouts for 4-wire Diode (Bipolar) and Resistor Temperature sensors, scattered throughout the chip -Verified the existing 13-bit W-2W current steering DAC (Tunerdac) with 400nA DNL, used to drive the resistive heaters that tune to the right photon wavelength Show less



Micron Technology

• United States
• Semiconductor Manufacturing
• 700 & Above Employee

• Analog/Mixed-signal design engineer

  • Jun 2018 - Jan 2020

  ------ Delay cells of a DLL (for read/write timing synchronization and PVT monitoring for SSD controller application) o Designed, verified, supervised layout and taped-out, a low DCD low Jitter, tunable delay cell to be used in a chain of inverters as a Delay line in an all- digital Delay-Locked Loop in 12nm FINFET TSMC technology to provide delay for clock/data for the read and write paths from memory. Operating frequency 400-800MHz (800M-1.6G transfer/s), max DCD generation of 2.5% in 128-tap chain (with +-5% input DCD) and small Period Jitter generation ------ GPIO o Designed, verified and supervised layout for General Rx/TX IO buffers used for JTAG and other low frequency application. Show less



MaxLinear

• United States
• Semiconductor Manufacturing
• 700 & Above Employee

• Senior RF/Mixed-signal design engineer

  • Oct 2016 - May 2018

  -----Clocking (5G receiver front-end application) o Designed and verified a Modular Regulator with better than 35dB PSR over PVT and over frequencies of 1MHz+ with 100pF cap per 0-10mA of output current, regulating 1.2V down to 0.8V, used locally to feed all post VCO and Clock Distribution Network o (Feasibility) Phase noise Calculations for RF Fractional-N PLL using Octave/MATLAB/VerilogA through noise profiles of all blocks o (Feasibility) PFD/Charge-pump design and evaluation used in RF PLL o (Feasibility) Clock distribution design and power estimate of both CML and CMOS for post VCO clocking -----Serializer/Deserializer (Optical transmitter SERDES application) o Designed and verified post layout 14:1 MUX-based 14GHz Serializer and DeSerializer, as well as the required logic to generate the required clock using LFSR in 16nm FINFET TSMC technology o Designed and performed timing verification on 500um/14GHz channel: -Used EMX to model clock/data routing as transmission lines, to quantify cross talk and distortion along the channel -Sized buffers and repeaters (re-timers) satisfying setup/hold time restrictions over the clock/data path in the channel Show less



Semtech

• United States
• Technology, Information and Internet
• 700 & Above Employee

• Analog Design Engineer

  • Jun 2014 - Sep 2016

  --- High-side Current sensing amplifier: -Developed and designed a High-side current shunt monitor with 4-40V supply and input common mode range and 0-4V output, gain of 50 and less than 100uV input referred offset, implemented using a chopper-stabilized amplifier to reduce the offset, robust against PVT and Mismatch --- Low-side Current sensing amplifier: -Designed accurate, high speed, low power, Low-Side current sense amplifier using differential common-gate amplifier topology for Boost converter for 0.7A to 10A input range for 3V to 5.5V supply range, and output ratio of 64k-to-1 --- Low Dropout Regulator (LDO) -Designed (and supervised layout) a 3.0V/50mA regulator with 3.5-6V input, with current limit (set to 100mA), 40dB supply rejection (at 300 kHz) and stabilized from no-load to full load and over PVT and Mismatch --- Bandgap -Designed (and supervised layout) a Brokaw bandgap circuit with 3.5-6V input and 1.2/1/0.6V output, 35dB supply rejection (at 300 kHz), stabilized and fully functional over PVT and Mismatch with Thermal Shut Down (TSD) --- Rail-to-rail Amplifier (buffer): -Designed a fast settling, low power, rail-to-rail operational amplifier with constant-gm (12%) using NMOS and PMOS complementary input transistors, folded cascode topology and class-AB output stage --- Chip Validation: -Thoroughly tested the aforementioned designed High-Side current sense/LDO/Bandgap chips, on the Bench, assuring functionality as well as parameter compatibility with the Datasheet -Explored the issue of high quiescent current, seen in 20% of Ultra-low power LDO units, through simulation followed by lab experiment using FIB circuit edit, verifying the anticipated root cause; Developed and implemented a circuit fix that completely resolved the issue in the next chip revision -Tested chips for Latch-up using Curve-Tracer/Parameter analyzer by current injection (I-Test) and Overvoltage tests Show less



The University of Texas at Dallas

• United States
• Higher Education
• 700 & Above Employee

• Teaching Assistant

  • Jan 2012 - May 2014

  --- PLL -Designed a 1920-1980MHz charge-pump Integer-N, frequency synthesizer Phase-Locked-Loop with reference frequency of 5 MHz, 1 V supply and 5MHz channel spacing in 65nm CMOS technology * Designed Phase frequency detector (PFD) using NOR gates, Charge-pump and RC Low Pass Filter, VCO with 3 stage ring VCO using differential pair with PMOS load delay cells with tuning range of 1700MHz to 2.1GHz, (also with LC-VCO), Frequency divided by 384-396 using pulse swallow divider * Simulated I) using behavioral models in Matlab-Simulink and Veriloga, II) using Cadence Ultrasim III) using transient simulation --- Inductor - Designed nested inductors of 40-50pH with mutual inductance simulated in HFSS to be used in the 200 GHz BFO LC-Oscillator in UMC65nm technology --- Low Dropout regulator: - Designed LDO regulator in TSMC 350nm technology meeting the following specs: Input supply 2V, Maximum output current 160mA, Dropout voltage 150mV, Quiescent current 40uA, Output Capacitor 3.3uF, ESR 0.5ohm, Loop gain 60dB, Maximum overshoot and undershoot 80mV --- Operational-amplifier - Designed and simulated a single-ended Folded-Cascode Op-amp: low-power (1.16mW@2.5V supply), 70+dB dc-gain, 10ns settling-time, high input/output voltage swing (from 1V to 2V), stabilized for optimum Phase margin (62 degrees) and Gain Margin (18 dB), robust against temperature range of 0 to 75 degrees Celsius, implemented in 250nm CMOS technology to be used as unity-gain buffer --- RFIC -Designed receiver front-end of a 4G wireless system (LTE): * Designed two stage cascode common source LNA with inductive source degeneration: 20 dB gain, -10 dBm IIP3 and 3dB NF * Designed single balanced active mixer: 5dB conversion gain, 10dB NF and 10dBm IIP3 * Designed LC cross-coupled oscillator: -130dBc at 1MHz offset Phase noise, 200MHz tuning range --- VLSI - Designed a PWM signal generator with 12-bits resolution (duty-cycle/dead-time inputs) Show less



Concordia University

• Canada
• Higher Education
• 700 & Above Employee

• Research Assistant

  • Dec 2009 - Dec 2010

  --- Process-invariant CML circuits -Proposed a scheme to overcome the effect of process variations in CML circuits using ring oscillators * Explored and quantified the impact of process variation on CML circuits (CML inverter with resistive as well as PMOS loads) using Monte-Carlo simulations and process corners * Proposed a method to fix this variation: A 3 stage ring oscillator is exposed to process variation whose amplitude of oscillation (as a tool to tune the DC-gain) is sensed by a Peak detector; this amplitude is compared to the nominal oscillation amplitude and the resistor/PMOS loads are tuned accordingly in a feedback loop to get the nominal amplitude * Reduced the variations in DC-gain and Delay beating the conventional method, i.e. the Replica bias Show less