Miten Chotaliya

Technical Lead, DFT at Eximius Design
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Contact Information
us****@****om
(386) 825-5501
Location
Ahmedabad, Gujarat, India, IN

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Experience

    • United States
    • IT Services and IT Consulting
    • 200 - 300 Employee
    • Technical Lead, DFT
      • Nov 2020 - Present

    • Staff Engineer, DFT
      • Oct 2018 - Oct 2020

    • United States
    • IT Services and IT Consulting
    • 700 & Above Employee
    • Senior DFT Engineer
      • Mar 2016 - Oct 2018

    • United States
    • Telecommunications
    • 700 & Above Employee
    • DFT Consultant
      • Apr 2014 - Mar 2016

    • India
    • Semiconductors
    • 1 - 100 Employee
    • DFT Engineer
      • Nov 2013 - Mar 2016

    • Switzerland
    • Semiconductor Manufacturing
    • 700 & Above Employee
    • DFT Engineer
      • Jul 2012 - May 2013

      Project : “Development of DFT for TMC IP in SoC" Description : Made the understanding on DFT basics,Techniques : Scan, ATPG and Boundary Scan/JTAG.Ramped up with ATPG Flow & shell/perl/tcl scripting.Hands on & responsible for ATPG pattern Generation & simulation of Stuck at and Transition fault models.Worked on Simulation debug for ATPG patterns and analysis on BSD sims. Also, performed simulation of memory BIST with and without PLL, BITMAP tests and verifying the bend and bbad signals of the same.Additionally Learned synopsys/custom OCC used for SoC IP.

Education

  • Institute of technology,NU Nirma University
    M.Tech, VLSI Design
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  • Ahmedabad Institute of Technology Gujarat University
    B.E, Electronics & communication
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  • GATE-2011
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