Experience

Cerebras Systems

• United States
• Computer Hardware
• 200 - 300 Employee

• Principal Engineer

  • Jan 2023 - Present

• Member Of Technical Staff

  • Apr 2021 - Jan 2023



Huawei

• China
• Telecommunications
• 700 & Above Employee

• Principal Engineer

  • Jun 2020 - Apr 2021

• Senior Staff Engineer

  • Jul 2019 - Jun 2020



Intel Corporation

• United States
• Semiconductor Manufacturing
• 700 & Above Employee

• Software Engineer

  • Jan 2016 - Jun 2019



Altera

• United States
• Semiconductors
• 700 & Above Employee

• Member of Technical Staff

  • Jun 2014 - Dec 2015

• Senior Design Engineer

  • Mar 2012 - Jun 2014

  - Timing and power modeling of GPIO buffers in all 28nm Altera FPGA families and beyond - Power modeling of IO-subsystem IPs: SerDes, EMIF



University of Waterloo

• Canada
• Higher Education
• 700 & Above Employee

• Research Assisstant

  • Sep 2008 - Jan 2012

  Research Assisstant of VLSI Group - Developed EDA solutions for advanced lithography technologies such as phase shift masking (PSM), double exposure (DE), and double patterning (DP) Research Assisstant of VLSI Group - Developed EDA solutions for advanced lithography technologies such as phase shift masking (PSM), double exposure (DE), and double patterning (DP)



Altera

• United States
• Semiconductors
• 700 & Above Employee

• Intern

  • Sep 2011 - Dec 2011



Mentor Graphics

• United States
• Software Development
• 700 & Above Employee

• Intern

  • May 2010 - Mar 2011

  - Conducted a simulation-based study to find manufacturability challenges in self-aligned double patterning (SADP) lithography - Proposed an ILP-based post-layout decomposition method to improve the litho-friendliness of layouts which are printed by SADP method - Implemented a heuristic partitioning-based algorithm to accelerate the proposed litho-friendly SADP decomposition method - Proposed and implemented a SADP-aware detailed routing engine to improve SADP-friendliness of the final layout in a correct-by-construction approach Show less



Amirkabir University of Technology (EDA Lab)

• Iran

• Research Assisstant & Software Engineer

  • Sep 2004 - Aug 2008

  - Implemented a layout netlist and parasitic extraction engine to be embedded in an industrial automated layout synthesis tool - Developed a GUI in QT-designer to view and edit a given layout - Proposed a statistical register placement and clock routing method to minimize the destructive clock skew in skew-scheduled designs - Proposed a multi-objective evolutionary algorithm to improve statistical yield loss in both combinational and sequential circuits using gate sizing, threshold assignment, and skew scheduling Show less