Experience

Cerebras Systems

• United States
• Computer Hardware
• 200 - 300 Employee

• Staff

  • Mar 2019 - Present

• Staff

  • Mar 2019 - Present

• Member Of Technical Staff

  • Mar 2019 - Present



Bossanova Robotics

• San Francisco Bay Area

• Senior Manager of HW Validation and Production Test Development

  • May 2017 - Present



DSSD

• Senior Test Development Engineer & NPI

  • Mar 2014 - Present



Violin Memory

• Santa Clara, CA

• Senior Test Development Engineer & NPI

  • Jun 2012 - Mar 2014

  Products: Flash Array, PCIe cards, Modular systems. Responsible for the development of Flash Array production test solution. • Worked cross functionally to define and drive manufacturing test requirements for NPI and production releases. • Responsible for the development of first generation PCIe flash array manufacturing and test processes. • Responsible for developing manufacturing test processes for data management products which employ the latest server… Show more Products: Flash Array, PCIe cards, Modular systems. Responsible for the development of Flash Array production test solution. • Worked cross functionally to define and drive manufacturing test requirements for NPI and production releases. • Responsible for the development of first generation PCIe flash array manufacturing and test processes. • Responsible for developing manufacturing test processes for data management products which employ the latest server technologies. • Designed and deployed a custom design test platform to robustly and efficiently support PCIe card volume production test at the CM. The solution involved innovative use of new mechanical designs and existing components. • Developed automated GUI and scripts to efficiently drive the hardware and report test results. Show less Products: Flash Array, PCIe cards, Modular systems. Responsible for the development of Flash Array production test solution. • Worked cross functionally to define and drive manufacturing test requirements for NPI and production releases. • Responsible for the development of first generation PCIe flash array manufacturing and test processes. • Responsible for developing manufacturing test processes for data management products which employ the latest server… Show more Products: Flash Array, PCIe cards, Modular systems. Responsible for the development of Flash Array production test solution. • Worked cross functionally to define and drive manufacturing test requirements for NPI and production releases. • Responsible for the development of first generation PCIe flash array manufacturing and test processes. • Responsible for developing manufacturing test processes for data management products which employ the latest server technologies. • Designed and deployed a custom design test platform to robustly and efficiently support PCIe card volume production test at the CM. The solution involved innovative use of new mechanical designs and existing components. • Developed automated GUI and scripts to efficiently drive the hardware and report test results. Show less



AMTED

• Operation Manager

  • Aug 2010 - Mar 2013

  Design and manufacture manufacturing test equipments, fixtures, thermal control, ... Design and manufacture manufacturing test equipments, fixtures, thermal control, ...



Brocade

• United States
• Computer Networking Products
• 700 & Above Employee

• Hardware development engineer, project lead

  • Sep 2005 - May 2009

  Responsibilities: Involvement: Design, cross functional management, sustaining, Locations: US, China Focus: JDM & ODM products Hardware design and validation engineer. Responsibled in the designing and verification of a few gen2 platforms. Area of involvement includes PCB and FPGA design. Developed and managed an Asia engineering team oversea which responsible in JDM class products design and sustaining. Worked with an ODM team in the US on new products… Show more Responsibilities: Involvement: Design, cross functional management, sustaining, Locations: US, China Focus: JDM & ODM products Hardware design and validation engineer. Responsibled in the designing and verification of a few gen2 platforms. Area of involvement includes PCB and FPGA design. Developed and managed an Asia engineering team oversea which responsible in JDM class products design and sustaining. Worked with an ODM team in the US on new products development. Coordinated and managed efforts amount customers, internal cross functional teams and CM both in the US and oversea. Show less Responsibilities: Involvement: Design, cross functional management, sustaining, Locations: US, China Focus: JDM & ODM products Hardware design and validation engineer. Responsibled in the designing and verification of a few gen2 platforms. Area of involvement includes PCB and FPGA design. Developed and managed an Asia engineering team oversea which responsible in JDM class products design and sustaining. Worked with an ODM team in the US on new products… Show more Responsibilities: Involvement: Design, cross functional management, sustaining, Locations: US, China Focus: JDM & ODM products Hardware design and validation engineer. Responsibled in the designing and verification of a few gen2 platforms. Area of involvement includes PCB and FPGA design. Developed and managed an Asia engineering team oversea which responsible in JDM class products design and sustaining. Worked with an ODM team in the US on new products development. Coordinated and managed efforts amount customers, internal cross functional teams and CM both in the US and oversea. Show less



Xilinx

• United States
• Semiconductor Manufacturing
• 700 & Above Employee

• New Product Characterization Engineer

  • Apr 2004 - Sep 2005

  Responsibilities included development of PCB and FPGA test patterns to accurately characterize peak and worst-case performance of all Virtex4 and Spartan3E device families. • Delivered several performance characterization PCB boards and thousands of test patterns. • Defined and created BIST for V4 to accurately test its internal DDR memory Fmax. • Defined and created bench automation to extensively test DCM jitter and IO Fmax, wherein significantly saving valuable test time on the ATE. Responsibilities included development of PCB and FPGA test patterns to accurately characterize peak and worst-case performance of all Virtex4 and Spartan3E device families. • Delivered several performance characterization PCB boards and thousands of test patterns. • Defined and created BIST for V4 to accurately test its internal DDR memory Fmax. • Defined and created bench automation to extensively test DCM jitter and IO Fmax, wherein significantly saving valuable test time on the ATE.



Brocade

• United States
• Computer Networking Products
• 700 & Above Employee

• Senior Hardware Engineer

  • Jul 2000 - Mar 2004

  Responsibilities included board/CPLD/FPGA developments, design verification lead and post release customer support for high-speed communication systems. Major contributor to the success of several released products including the SW2800E, SW3900, and SW24000. 3 of 2  Re-designed CPLDs and FPGA to provide private inter-blades communication channels to significantly improve robustness and performance over a previous generation product.  Participated in cost reduction designs of a back… Show more Responsibilities included board/CPLD/FPGA developments, design verification lead and post release customer support for high-speed communication systems. Major contributor to the success of several released products including the SW2800E, SW3900, and SW24000. 3 of 2  Re-designed CPLDs and FPGA to provide private inter-blades communication channels to significantly improve robustness and performance over a previous generation product.  Participated in cost reduction designs of a back plane and a sub-system that lowered production cost by more than 50%.  Proposed and created system functional simulation using Verilog HDL to allow early detection of board level design flaws and to ensure inter-blade connectivity and logic robustness.  Developed extensive system verification plan to ensure testing and meeting all required AC/DC characteristics. Analyzed result for signal integrity improvement and minimize adverse trace reflections. Show less Responsibilities included board/CPLD/FPGA developments, design verification lead and post release customer support for high-speed communication systems. Major contributor to the success of several released products including the SW2800E, SW3900, and SW24000. 3 of 2  Re-designed CPLDs and FPGA to provide private inter-blades communication channels to significantly improve robustness and performance over a previous generation product.  Participated in cost reduction designs of a back… Show more Responsibilities included board/CPLD/FPGA developments, design verification lead and post release customer support for high-speed communication systems. Major contributor to the success of several released products including the SW2800E, SW3900, and SW24000. 3 of 2  Re-designed CPLDs and FPGA to provide private inter-blades communication channels to significantly improve robustness and performance over a previous generation product.  Participated in cost reduction designs of a back plane and a sub-system that lowered production cost by more than 50%.  Proposed and created system functional simulation using Verilog HDL to allow early detection of board level design flaws and to ensure inter-blade connectivity and logic robustness.  Developed extensive system verification plan to ensure testing and meeting all required AC/DC characteristics. Analyzed result for signal integrity improvement and minimize adverse trace reflections. Show less



Faroudja Laboratories, Inc.

• Design Engineer

  • Apr 1999 - Jul 2000

  Responsibilities included FPGA design and simulation using Verilog for the first 1080p video transcoder. Board level design and debug were also practiced extensively. Responsibilities included FPGA design and simulation using Verilog for the first 1080p video transcoder. Board level design and debug were also practiced extensively.



VTEL/CLI INC.

• Hardware Design Engineer

  • Apr 1996 - Mar 1999