Senior Technical Software Systems Designer

• Apr 2023 - Present

Member Of Technical Staff - Silicon Realization Group

• Jun 2022 - Jan 2023

Senior FPGA Designer

• Jul 2020 - Jun 2022

The designer in me wanted more air time, so, I transitioned back to an individual contributor role.On the digital logic side, responsible for creating RTL designs for FPGAs. For example, an AXI4 based, XTS-AES encryption/decryption core. Routinely perform peer reviews at the system and block level, contribute to process development, assist with interviews and co-op evaluations.On the SW side, responsible for the planning and development of a web based development tool using Javascript, Python, Apache, PostgreSQL and Redis. Show less

FPGA Engineering Manager

• May 2017 - Jul 2020

Managed a team of 12-15 FPGA design and verification developers.Main responsibilities included task assignment, design review and sign-off, process development, estimations to support bids, tools and license planning, recruitment/retention, performance reviews, compensation reviews and training.

Senior FPGA Designer

• Apr 2011 - May 2017

As a developer, I performed front to back FPGA development that included FPGA top level, control and image processing blocks (e.g. image warper computation, non-uniformity correction, bad-pixel replacement). Requirements capture and conceptual design, detailed architectural design, documentation development, RTL coding, verification (in simulation and in system), prepared and presented material at review gates, release to production activities.As a team member, I was involved in process development, tool development, peer reviewing the designs of others, mentoring more junior staff and providing training (co-developed course on FPGAs and a self-developed course on Python). Show less

Product Architect

• May 2010 - Apr 2011

Development lead for a 2D Graphics Accelerator targeting the DirectFB API, Raster Operators (ROPs), blitting, rotating, scaling etc. Responsible for use-case definition and associated memory bandwidth assessment for the Baseband Video Platform used in the company's secure media processor products. Lead the development of a more structured but lightweight project management system. Development lead for a 2D Graphics Accelerator targeting the DirectFB API, Raster Operators (ROPs), blitting, rotating, scaling etc. Responsible for use-case definition and associated memory bandwidth assessment for the Baseband Video Platform used in the company's secure media processor products. Lead the development of a more structured but lightweight project management system.

Senior ASIC Design Engineer

• Feb 2008 - May 2010

Hardware design prime on a 400MHz DSP design. Developed top level architecture suitable for ASIC and FPGA implementations; performed task assessment, schedule development, resource assignment and die size estimation; tracked and reported progress to management team; independently specified, architected and coded sub blocks Performed FPGA synthesis / STA on high gate count designs. Execute system level (scenario) verification for an ASIC tape-out. Documented the set of key system level configurations for testing; wrote and executed test cases; performed debugging; guided other engineers in building, executing and debugging test cases; tracked and reported progress. Independently proposed and assisted with methodology improvements. Show less

Senior ASIC Design Engineer

• Jul 1998 - Feb 2008

Design prime on chip level development of multiple image processing products overseeing chip level architecture, resource assignments, scheduling, block level specification development, block level architecture development and mentoring of more junior engineers. Independently carried out specification, architecture, coding, verification and in-lab characterization of key image processing blocks for several image processors. Experience with Verilog, VHDL, TCL, C/C++/C#, VB, ModelSIM/Questa, Design Compiler, Prime Time and Magma Blast Create. Show less