Meng Jhe Wu
Senior Engineer at 奇景光電股份有限公司- Claim this Profile
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Bio
Experience
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奇景光電股份有限公司
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Taiwan
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Appliances, Electrical, and Electronics Manufacturing
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1 - 100 Employee
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Senior Engineer
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Apr 2017 - Present
CDR Design 1.8Gbps/3Gbps (0.18um) (ISP interface) Mini-LVDS RX Design (330Mbps) CDR Design 1.8Gbps/3Gbps (0.18um) (ISP interface) Mini-LVDS RX Design (330Mbps)
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智原科技
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China
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IT Services and IT Consulting
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Senior Engineer
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Jul 2009 - Mar 2017
PLL/DLL Design (0.153um~28nm) USB2.0 TXPLL Design (0.11um) USB3.0 TXPLL Design (5GHz) (40nm) MIPI DPHY TXPLL Design (3GHz) (40nm) V-by-One TXPLL Design (4GHz) (40nm/28nm) FPD-Link DLL Design (16M~180MHz) (40nm/28nm) PLL/DLL Design (0.153um~28nm) USB2.0 TXPLL Design (0.11um) USB3.0 TXPLL Design (5GHz) (40nm) MIPI DPHY TXPLL Design (3GHz) (40nm) V-by-One TXPLL Design (4GHz) (40nm/28nm) FPD-Link DLL Design (16M~180MHz) (40nm/28nm)
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茂德科技
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1 - 100 Employee
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Junior Engineer
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Mar 2008 - Jun 2009
Reverse circuit (DDRII Power Circuit) DDRII Circuit Simulation and Analysis Memory Component Testing Reverse circuit (DDRII Power Circuit) DDRII Circuit Simulation and Analysis Memory Component Testing
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Education
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國立中央大學
碩士, 電機工程學系