Mehdi Shiri

FPGA Design Engineer at HexoSys Group
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Contact Information
us****@****om
(386) 825-5501
Location
Kuala Lumpur, Federal Territory of Kuala Lumpur, Malaysia, MY
Languages
  • Persian Full professional proficiency
  • Turkish Professional working proficiency
  • English Professional working proficiency

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Ahmad Sammak

‘Ridiculously efficient’ is the phrase that comes to mind when I think about Mehdi. I have had a fantastic experience of working with Mehdi for about two years as the co-worker. Although we have not work on the same projects, I have learned many from he in all aspects of FPGA design. He is a very talented person and can manage project efficiently and offer the best solution to any problem. As a team member or a leader, Mehdi earns my highest recommendation.

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Experience

    • Malaysia
    • Computer Hardware Manufacturing
    • 1 - 100 Employee
    • FPGA Design Engineer
      • Oct 2016 - Present

      As a senior programmer, I participate in a team that develops the Ethernet and Fiber Channel analyzer of Teledyne Lecroy. This position requires complete mastery of the concepts of different protocols. As a senior programmer, I participate in a team that develops the Ethernet and Fiber Channel analyzer of Teledyne Lecroy. This position requires complete mastery of the concepts of different protocols.

    • Iran
    • Broadcast Media Production and Distribution
    • 1 - 100 Employee
    • FPGA designer
      • Feb 2015 - Sep 2016

      Digital hardware designing and programming for FPGA chipsHigh-speed serial communications (Such as RapidIO) And transporting HD-SDI video on RapidIOAudio processing (Like as Audio sample rate converter, AES receiver, and transmitter.and Audio delayer)Experience at Video processing (2-D video switch transition effect (such as v-fade, x-fade) for HD-SD video resolutions, Luma video keyer & logo inserting)Video & audio decoder implementation:(In this project, video decoding process is done by the processor but CRC and EDH inserting, Audio embedding and synchronization is implemented in FPGA. Also, the video is displayed with HD-SDI interface by FPGA).Video & audio encoder implementation:(In this project, the video and audio captured by different sources and after multiplexing are delivered to the encoder. And encoded TS is routed to output with ASI.)MPEG-TS PCR error fixer implementation:(Some of the encoders don't have good efficiency and their outputs may have significant errors. I fixed PCR accuracy, PCR interval and continuity errors of TS stream.)

    • IT Services and IT Consulting
    • 1 - 100 Employee
    • Digital Electronic Designer
      • Feb 2013 - Feb 2015

      scrambler and descrambler: (BISS scrambler for MPEG-TS stream ) ETR-290 Based TS Analyzer IP and Network ( VoIP, ...) Multimedia Processing :Low resource implementing of Frame-synchronizer.Audio embedder.Video re-sizing & scaling.Video format converter.Audio level meter, SPDIF receiver. scrambler and descrambler: (BISS scrambler for MPEG-TS stream ) ETR-290 Based TS Analyzer IP and Network ( VoIP, ...) Multimedia Processing :Low resource implementing of Frame-synchronizer.Audio embedder.Video re-sizing & scaling.Video format converter.Audio level meter, SPDIF receiver.

    • Digital Electronic Designer
      • Feb 2012 - Feb 2013

      FPGA implementing of digital monitors.Monochrome video processing FPGA implementing of digital monitors.Monochrome video processing

Education

  • iran university of science and technology
    Master's degree, Mixed signal
    2009 - 2012
  • iran university of science and technology
    Master's degree, Electrical, Electronics and Communications Engineering
    2008 - 2011

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