Experience

HexoSys Group

• Malaysia
• Computer Hardware Manufacturing
• 1 - 100 Employee

• Hardware Design Engineer

  • Aug 2015 - Present

  RTL design for MiPi Uniport , USB 3.2 ,USB 3.1Working with high-speed multi-gigabit transceivers Optimizing RTL designsValidating FPGASystemVerilog based Verification Bringing-Up hardware boards Develop Python scripts RTL design for MiPi Uniport , USB 3.2 ,USB 3.1Working with high-speed multi-gigabit transceivers Optimizing RTL designsValidating FPGASystemVerilog based Verification Bringing-Up hardware boards Develop Python scripts



HCLTech

• India
• IT Services and IT Consulting
• 700 & Above Employee

• Design and Verification Engineer

  • Oct 2013 - Aug 2015

  Developing UVM based testbench, FGPA(VC707) based designing and debugging, writing embedded software for FPGA. Perl and TCL scripting . DDR3 ,SATA3, XAUI.RTL design for kintex7 family, RTL design for XAUI to SATA3 converter, extensive experience with vivado synthesis and implementation and have good knowledge to debug FPGA timing issues(virtex7 & kintex7)

• Member technical staff

  • Mar 2012 - Oct 2013

  Developing testbenches, writting perl script which generates testcases of various scenarios, simulating and debugging



Aizyc

• India
• Staffing and Recruiting
• 1 - 100 Employee

• Design and verification engineer

  • May 2011 - Feb 2012

  Developing testbenches and testcases, linting, simulation and debugging, timing simulations Developing testbenches and testcases, linting, simulation and debugging, timing simulations



Maven Silicon

• India
• Semiconductor Manufacturing
• 700 & Above Employee

• ASIC trainee

  • Oct 2010 - Mar 2011

  Training in SystemVerilog Training in SystemVerilog