Martin Parenica
Chip IP Design Engineer at TTTech- Claim this Profile
Contact Information
us****@****om
(386) 825-5501
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Location
CZ
Languages
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Czech Native or bilingual proficiency
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English Professional working proficiency
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German Elementary proficiency
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Credentials
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Design For Six Sigma, Green Belt Certification
Honeywell -
First Certificate in English (FCE), March 2009
Cambridge ESOL
Experience
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TTTech
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Austria
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Computer Networking Products
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200 - 300 Employee
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Chip IP Design Engineer
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Feb 2012 - Present
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Honeywell
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United States
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Appliances, Electrical, and Electronics Manufacturing
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700 & Above Employee
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ASIC/FPGA Engineer
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Oct 2007 - Feb 2012
FPGA development and verification in aerospace industry (DO-254): - defining requirements, design HDL coding, synthesis, P&R - defining simulation testbenches & coding in VHDL and SystemVerilog / OVM - defining test cases and coding test procedures - scripting in Perl and Bash - global team work experience FPGA development and verification in aerospace industry (DO-254): - defining requirements, design HDL coding, synthesis, P&R - defining simulation testbenches & coding in VHDL and SystemVerilog / OVM - defining test cases and coding test procedures - scripting in Perl and Bash - global team work experience
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Education
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2008 - 2009
TLC-Top Language Centre
FCE Cambridge exam preparation -
2005 - 2007
Brno University of Technology
Master, Computer Systems and Networks -
2002 - 2005
Brno University of Technology
Bachelor, Information Technology
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