Experience

CoreHW

• Finland
• Semiconductor Manufacturing
• 1 - 100 Employee

• Senior Digital Design Engineer

  • Mar 2018 - Present

  - Digital design flow development - Architecture and RTL development - Digital design verification - Synthesis, Place and Route, Timing Closure - AMS simulation - Analog block real number modelling using SystemVerilog - Digital design flow development - Architecture and RTL development - Digital design verification - Synthesis, Place and Route, Timing Closure - AMS simulation - Analog block real number modelling using SystemVerilog


MediTerveys Oy
• CEO / Co-Founder

  • Nov 2018 - Present


LG Electronics

• South Korea
• Computers and Electronics Manufacturing
• 700 & Above Employee

• Senior Research Engineer

  • Jul 2015 - Feb 2018

  - Architecture and IP development for different IPs. -From specification to implementation including UVM based random verification, design packaging and release management. - Mainly focused on interface designs from ultra-high-speed to ultra-low-power. - Architecture and IP development for different IPs. -From specification to implementation including UVM based random verification, design packaging and release management. - Mainly focused on interface designs from ultra-high-speed to ultra-low-power.



Nordic Semiconductor ASA

• R&D Engineer

  • Apr 2015 - Jun 2015

  IP development including RTL and verification. IP development including RTL and verification.



Ericsson

• Sweden
• Telecommunications
• 700 & Above Employee

• Senior Design Engineer

  • Aug 2013 - Mar 2015

  - Architecture and IP development for ultra-high-speed and low-power mobile chip interface. From specification to implementation including UVM based random verification, design packaging and release management. - Power-Aware and power estimation simulation and analysis. - Laboratory testing and product support for SW development. - Architecture and IP development for ultra-high-speed and low-power mobile chip interface. From specification to implementation including UVM based random verification, design packaging and release management. - Power-Aware and power estimation simulation and analysis. - Laboratory testing and product support for SW development.



ST-Ericsson

• Switzerland
• Semiconductor Manufacturing
• 500 - 600 Employee

• Design engineer

  • Feb 2009 - Aug 2013

  - ARM processor based subsystem and IP development from specification to RTL including structural verification, design packaging and release management. - Top level interconnect design and integration. - Coverage-driven constrained random verification for subsystems and interconnects. - Power estimation and analysis for low power design. International assignment, Grenoble, France 05/2010 – 08/2010 During this period of time I had an essential role in a special team that was responsible for adapting a new design tool. Thereafter the tool was taken widely into use within the company. Working in a multicultural environment in a development project was equally challenging and rewarding. Afterwards I was also responsible for supporting various projects using this tool.


ST-NXP Wireless
• Semiconductors
• 1 - 100 Employee
• Design engineer

  • Aug 2008 - Jan 2009

STMicroelectronics
• Switzerland
• Semiconductor Manufacturing
• 700 & Above Employee
• Design engineer

  • Jun 2008 - Jul 2008


Nokia

• Finland
• Telecommunications
• 700 & Above Employee

• Trainee

  • May 2007 - Aug 2007

  ASIC structural and functional verification. ASIC structural and functional verification.