Marco Habernegg

Head of Project Management – Chip Development at TTTech
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Contact Information
us****@****om
(386) 825-5501
Location
Vienna, Vienna, Austria, AT
Skills

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Credentials

  • Generative AI Overview for Project Managers
    Project Management Institute
    Sep, 2023
    - Nov, 2024
  • STRATEGIC MARKETING AND CUSTOMER EXPERIENCE USING THE F4P FRAMEWORK
    David J Anderson School of Management
    Jun, 2023
    - Nov, 2024
  • Agile Hybrid Project Pro
    Project Management Institute
    Aug, 2022
    - Nov, 2024
  • Flight Levels Systems Architecture
    Flight Levels Academy
    Dec, 2021
    - Nov, 2024
  • Certified Agile Leadership
    Agile Leadership Journey
    Jun, 2021
    - Nov, 2024
  • Kanban Management Professional
    Kanban University
    Jul, 2020
    - Nov, 2024
  • ISTQB® Certified Tester Advanced Level - Test Manager
    ISTQB - International Software Testing Qualifications Board
    Sep, 2019
    - Nov, 2024
  • Certified Professional for Requirements Engineering
    IREB GmbH
    Aug, 2019
    - Nov, 2024
  • PMI Agile Certified Practitioner (PMI-ACP)®
    Project Management Institute
    Sep, 2017
    - Nov, 2024
  • Project Management Professional (PMP)®
    Project Management Institute
    Jun, 2017
    - Nov, 2024
  • PMI Risk Management Professional (PMI-RMP)
    Project Management Institute
    Jan, 2022
    - Nov, 2024
  • Disciplined Agile Senior Scrum Master (DASSM)
    Project Management Institute
    Jul, 2023
    - Nov, 2024
  • Certified LeSS Practitioner
    The LeSS Company
    Apr, 2019
    - Nov, 2024
  • Certified Scrum Product Owner® (CSPO®)
    Scrum Alliance
    Apr, 2018
    - Nov, 2024
  • Certified ScrumMaster® (CSM®)
    Scrum Alliance
    Jul, 2012
    - Nov, 2024
  • Certified SAFe® 4 Agilist
    Scaled Agile, Inc.
    Nov, 2018
    - Nov, 2024

Experience

  • TTTech
    • Austria
    • Computer Networking Products
    • 200 - 300 Employee
    • Head of Project Management – Chip Development
      • Dec 2020 - Present

      Team development; Service- and process optimization; Strategic project roadmap planning

    • Senior Project Manager
      • Jun 2017 - Present

      End-to-end project responsibility for the Design, Verification & Validation, Certification Liaison and Productization of certifiable SoCs targeting aviation (DO-254 DAL A), space and in-vehicle networking markets.

  • FH Joanneum
    • Austria
    • Higher Education
    • 200 - 300 Employee
    • Lecturer
      • Feb 2013 - May 2017

      Electronic systems @department of automotive engineering. Electronic systems @department of automotive engineering.

  • NXP Semiconductors Austria
    • Austria
    • Semiconductors
    • 200 - 300 Employee
    • Senior Digital Design Lead Engineer
      • Oct 2012 - May 2017

      Managing the creation process of SoCs focusing on the digital area. Modelling and implementation of digital architectures.

    • Digital Design Engineer
      • May 2004 - Sep 2012

    • Physical Design Engineer
      • May 2000 - Apr 2004

Education

  • Karl-Franzens-Universität Graz
    Master of Business Administration (MBA), Change Management
    2013 - 2015
  • Technische Universität Graz
    Dipl.-Ing., Telematik (Information and Computer Engineering)
    2005 - 2009
  • FH CAMPUS 02
    Dipl.-Ing. (FH), Automation Technology
    2001 - 2005

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