Experience

Sventl Asia Pacific

• Singapore
• Semiconductors
• 1 - 100 Employee

• DFT Engineer

  • Feb 2021 - Present

   SCAN Insertion and DRC analysis at block and chip level.  Regression failure debug in Scan validation.  Scan coverage improvement.  ATPG DRC analysis at the block and chip level.  Analysis and debugging of ATPG simulations (Timing and No-timing).  Detailed coverage analysis for coverage improvement.  Pattern generation for block level and multi-partition level Create and validate the environment setup and debug the issue related to DFT flow.  Debug and fixing… Show more  SCAN Insertion and DRC analysis at block and chip level.  Regression failure debug in Scan validation.  Scan coverage improvement.  ATPG DRC analysis at the block and chip level.  Analysis and debugging of ATPG simulations (Timing and No-timing).  Detailed coverage analysis for coverage improvement.  Pattern generation for block level and multi-partition level Create and validate the environment setup and debug the issue related to DFT flow.  Debug and fixing the issues present in DFT configuration and setup scripted files.  Supported DFT code-related enhancements like dft_netlist_checker and dft_coverage_utilities.  Reporting tool issues to vendors.  Responsible for Pandora setup to run DFT regression of different real time project simultaneously Created tcl script for extracting data from varies files and get the output in a specific pattern.  Modified the above script to create libverify.do file for automation.  Created a script for extracting data from the path links into a single file for the required specifications. Show less  SCAN Insertion and DRC analysis at block and chip level.  Regression failure debug in Scan validation.  Scan coverage improvement.  ATPG DRC analysis at the block and chip level.  Analysis and debugging of ATPG simulations (Timing and No-timing).  Detailed coverage analysis for coverage improvement.  Pattern generation for block level and multi-partition level Create and validate the environment setup and debug the issue related to DFT flow.  Debug and fixing… Show more  SCAN Insertion and DRC analysis at block and chip level.  Regression failure debug in Scan validation.  Scan coverage improvement.  ATPG DRC analysis at the block and chip level.  Analysis and debugging of ATPG simulations (Timing and No-timing).  Detailed coverage analysis for coverage improvement.  Pattern generation for block level and multi-partition level Create and validate the environment setup and debug the issue related to DFT flow.  Debug and fixing the issues present in DFT configuration and setup scripted files.  Supported DFT code-related enhancements like dft_netlist_checker and dft_coverage_utilities.  Reporting tool issues to vendors.  Responsible for Pandora setup to run DFT regression of different real time project simultaneously Created tcl script for extracting data from varies files and get the output in a specific pattern.  Modified the above script to create libverify.do file for automation.  Created a script for extracting data from the path links into a single file for the required specifications. Show less



CAVIUM NETWORKS (INDIA) PRIVATE LIMITED

• India
• 1 - 100 Employee

• DFT/Digital IC Design Engineer

  • Jul 2019 - Jan 2020

  I worked as DFT/Digital IC Design Engineer at Cavium Network Pvt Ltd which is a subsidiary of Marvell Semiconductors Pvt Ltd. (July ’19 – Jan ’20). I worked on Full-chip level Memory BIST pattern generation, simulation and debug I worked as DFT/Digital IC Design Engineer at Cavium Network Pvt Ltd which is a subsidiary of Marvell Semiconductors Pvt Ltd. (July ’19 – Jan ’20). I worked on Full-chip level Memory BIST pattern generation, simulation and debug