Sr. Manager

• Jun 2017 - Present

Hired in as Principal FPGA Engineer at Velodyne Labs with Algorithms/DSP group. Currently Sr. Manager, Embedded Systems. Hands-on coding R&D for flagship rotational & directional Lidars: • Wrote RTL & C code in areas such as motor control, power control, signal processing, filtering, anti-alias algorithm, interference mitigation, image quality improvements, eye safety, optical artifact reduction. Was technical lead for detector, then for entire sensor firmware. • Wrote Python & C code for SDK, as well as HTML/JS for Web UI. • Developed math model (wrote Octave/Matlab code) for sensor behavior as # of sensors scaled, with experimental lab component. • Derived analysis for new ASIC feature pre-tapeout. • Derived statistical modeling method associated with customer RMA and yield issue. • Two patents filed. Managed direct reports: RTL design, validation, and embedded C. Mentored new generation of engineers as many left after company became public. Developed functional safety architecture, turned wish lists into actionable code implementation. Managed JIRA tickets; ran weekly project meetings. Led team in triaging yield issues. Led RTL & C development for improved manufacturing variation tolerance. Derived new R&D approach to catch problems quickly and iterate (fail) fast; drove cross functional adoption. Instrumental in new product R&D and first customer shipment hitting schedule where I led the firmware development. Served as a primary technical interface in weekly customer call. Worked with customer-side architect to address issues associated with 1000+ shipped units. Managed multiple product pedigrees, releases, field upgrades and manufacturing compatibility issues. Instrumental in 100M+ USD investment deal. Performed security analysis and deriving security architecture. Wrote C code and brought up TPM and TLS security stack for embedded processor. Received Hero Award (quarterly employee award). Show less

Research Affiliate

• 2012 - 2018

Brought industrial perspective to MIT PhD research associated with error coding, manufacturing variation, security protocols, signal processing, and hardware security. Directed Bavaria/California research collaboration, including providing inputs to PhD research for Technical University Munich (TUM) information security lab and Fraunhofer AISEC (German gov't affiliated security lab). Received PhD based on a research career from KU Leuven as a part of COSIC crypto group. PhD defense panel: o Ingrid Verbauwhede, Advisor (COSIC/KU Leuven) o Srinivas Devadas, Advisor (CSAIL/MIT, former associate head EECS/MIT) o Bart Preneel (COSIC/KU Leuven, former president of Int’l Assoc. for Cryptologic Research) o David M’Raihi, Advisor (founding member, Gemplus Crypto Team; Apple, Pure Storage) o Matthias Hiller (Deputy Head of Hardware Security, Fraunhofer AISEC German security lab) 2500+ citations, 30+ publications. Received best paper award and best presenter award. Served as reviewer for scores of IEEE journals and papers. Served as program committee member for several security conferences including CHES. My code, algorithms, patents are a part of secure boot feature for 16nm and 7nm ARM SoCs. Design underwent functional safety and security review. Led defense of design (security review) with scores of security experts. Work underwent vetting by security experts in France, Germany, Belgium, and USA and is in mass production, with SoCs generating 100s of millions USD in revenue. Show less

Chief Scientist

• 2007 - 2017

Chief Architect for PUF-Enhanced Cryptographic ASIC. Started as Sr. ASIC Design Engineer (was first ASIC designer hire), and later Technical Director. • Algorithm to implementation derivation: RTL coding from scratch, synthesis, verification (entropy extractor, error correction, AES, Galois arithmetic, ARM APB interface, bridges, syndrome computation, euclidean solver computing error polynomial via GCD, Galois factoring via Chien search, max likelihood soft decision). • Personally coded designs from scratch that targeted ASIC tapeout at 0.13u, 28nm, 16nm and 7nm including ARM SoC for secure firmware load during boot. Xilinx FPGA implementations (V4, V5, S6, 7s). Used Verilog, c, Matlab. • Guided physical design, DFT/ATPG, CDC, LINT, timing closure, SPICE sim. • Wrote DPA selection functions, explored leakage modes; security review w/ experts. Machine learning attacks using RPROP neural networks. • Implemented directed tests, developed methodology for randomized testing, wrote cycle accurate model (SystemC, Linux). • Circuit level designs (gate/transistor); GDSII review. Co-developed specialized SPICE flow to reduce risk. • Pulled together diverse teams: digital design, circuit design, mathematics, systems engineering, verification, emulation, firmware engineering, DFT/ATPG, SPICE simulation, timing analysis, GDSII layout, silicon validation, reliability and stress testing. • Extensive experience working with customers, lawyers, VCs. Performed technical due diligence for Vinod Khosla for his VC investments. • Wrote Javascript/PHP code for AWS, and managed SW engineers to develop cloud-based authentication service and analytics, including geo-location & maps using Google API. • Extensive silicon characterization, system bring-up, algorithm development, Verilog coding, modeling, error correction experience, including reliability characterization & stress testing. Results published with IEEE, and in mass-production in TSMC 16nm & 7nm ARM SoC. Show less

Manager, R&D Engineering

• 2004 - 2007

Development of digital wireless radio using ARM CPU, FPGA, Ghz RF (up to 14Ghz). 60+Mcps datarate, up to 190Mhz clocks, multiple clock domains, clocking modes, multi-rate DSP. Instrumental in achieving 1st customer shipments, successful field trials. Wrote VHDL, c, Matlab code. ALGORITHM & DIGITAL BASEBAND FPGA RTL: Analysis, filter design using Matlab and C; VHDL coding of carrier recovery (CORDIC/CORDISC iterative numerical methods) and timing recovery loops, interpolators (cascaded halfband, 3x), decimators (cascaded half-band), pulse shaping filters (RRCOS), framer / deframer (including phase search), clocking circuitry (tx=tx, tx=rx, tx=int), clock synthesis (DCM/NCO). ARM CPU SOFTWARE: Coding of C on ARM CPU to control FPGA (carrier search and acquisition, tx power control, rx AGC, etc.) and other ICs: DDS, L-band Synthesizers, modulators, demodulators, serial port, 485/422 port and ECC. SYSTEM DESIGN & CHARACTERIZATION: Anti-imaging / anti-alias filter, DAC/ADC controls, clock synthesis (DDS), analog and direct IF design, AGC design, RF impedance matching. Coded production test automation using LabWindows CVI. Phase noise, carrier stability, temperature stability, vibration, BER tests, pull-in range, hold-in range, carrier interference, anti-jamming and anti-eavesdropping resistance. Supervised system board development, GHz RF modules, higher level sw. Trained and handed off tasks to new team members. Show less

Sr. Design Engineer / Applications Engineering

• 1997 - 2004

ASIC DESIGN: RTL coding (Verilog), synthesis (DC), verification (VCS/C/C++/Perl/Unix), timing closure (PrimeTime), gate-level simulation, floorplanning, emulation, chip bring-up, post-silicon validation, customer support, production test engineering (ATE), test vector generation, cost reduction. 7 IC design cycles, with millions of production ICs shipped. Included RTL for display processing, multi-rate DSP controls, memory bandwidth management. 3 patents granted. BOARD DESIGN: Specification, schematic capture (Orcad), signal integrity simulation (Hyperlinx), floor planning, trace/layer planning, parts selection, interface w/ layout/assembly house. 4 Board designs: hands-on design of 3 boards (24-layer multi-FPGA emulation; set-top box platforms); supervised design of 1 board for production test engineering (ATE). SOFTWARE DEVELOPMENT: Embedded software (BSP) for set-top boxes (C/VxWorks/Linux), API for PVR module (channel search, video encode). Targeted technology nodes: .35u, .25u, .18u, .13u, 90nm TSMC. HDTV decoder, Internet TV IC, Personal Video Recoder (PVR) Controller, HDTV/MIPS SoC, Dual MIPS SoC, ATSC SoC. Designs up to 10M gates. System Designs: Set-top Boxes, Personal Video Recorder, Conditional Access. Employee of the Quarter (Q2, 2004), selected from 800+ employees. Show less

VLSI Design Engineer, Hardware Systems Engineer

• 1997 - 2002

Acquired by Oak, then by Zoran. See Zoran description. Acquired by Oak, then by Zoran. See Zoran description.

ASIC Verfication

• 1996 - 1996

Gigabit Networking

• 1995 - 1995

Gigabit Networking Research

• 1994 - 1995

Systems Engineering (MPEG, Satellite Broadcasting)

• 1993 - 1994