Experience

Uptime Labs

• United Kingdom
• Technology, Information and Internet
• 1 - 100 Employee

• Artificial Intelligence

  • Oct 2022 - Present

  London, England, United Kingdom Innovate UK transformative technologies AI-powered immersive solutions



Shyld AI

• United States
• Hospitals and Health Care
• 1 - 100 Employee

• AI Engineering

  • Jun 2021 - Present

  San Francisco Bay Area Automatic infection control for indoor spaces. Co-led ROS + CV dev of Shyld AI's edge semi-robot product, AirSani. A Shimadzu partner.



SATIS.AI

• United Kingdom
• Software Development
• 1 - 100 Employee

• ML/IoT Specialist

  • Jun 2020 - May 2021

  London, England, United Kingdom Satis.AI is the full stack AI operating system for kitchens. Worked closely with Mo (ex Data director at Babylon health and a friend from Uni Manchester) to prototype application of AI into cooking processes and give actionable feedback to staff in real time. #AI #Real-time #ComputerVision



Headlight AI

• United Kingdom
• Utilities
• 1 - 100 Employee

• Head of AI

  • Feb 2019 - Apr 2020

  London, United Kingdom At Headlight AI : - Responsible for building AI systems used for real-time anomaly detection applications across company projects in rail, water and AV/Robotics - Led company's SaaS based projects on AWS marketplace.



Babylon Health

• United Kingdom
• Pharmaceutical Manufacturing

• AI Research (Contract)

  • Jul 2018 - Sep 2018

  London, United Kingdom Worked on a prototype for accelerating AI services incl. knowledge extraction and graph processing. The reinforcement of GDPR in 2018 posed challenges and obstacles to the successful implementation of acceleration pipelines in the cloud particularly F1.



Reconfigure.io

• United Kingdom
• IT Services and IT Consulting

• Co-Founder

  • Feb 2016 - Jun 2018

  Manchester, England, United Kingdom Executed my PhD research as an acceleration service under supervision of Professor Steve Furber of University of Manchester. An AWS F1 partner. Received £500k investment from UKFAST cloud provider to accelerate AI/Network services across their platform.



The University of Manchester

• United Kingdom
• Higher Education
• 700 & Above Employee

• EPSRC Doctoral Prize Fellow

  • Dec 2015 - Dec 2017

  Manchester Area, United Kingdom In my EPSRC fellowship project, advised by Prof. Steve B. Furber, I exploited the framework developed in my PhD to explore a new direction in architectural synthesis. Under my fellowship I collaborated with several international institutes including IHP, USC VLSI Labs and BSC in Barcelona to conduct global research on the directed synthesis paradigm. Later the technology filed fora US patent. According to EPSRC’s portfolio of research, this project falls under the most growing research… Show more In my EPSRC fellowship project, advised by Prof. Steve B. Furber, I exploited the framework developed in my PhD to explore a new direction in architectural synthesis. Under my fellowship I collaborated with several international institutes including IHP, USC VLSI Labs and BSC in Barcelona to conduct global research on the directed synthesis paradigm. Later the technology filed fora US patent. According to EPSRC’s portfolio of research, this project falls under the most growing research subject of “Energy Efficiency” which aims to achieve an energy reduction of 26-43% by exploiting ICT to achieve operability, control and visibility capability increases. My aim in developing an efficient design paradigm supports this strategy.

• PhD Researcher

  • Jul 2012 - Dec 2015

  Manchester, United Kingdom I'm a member of the Advanced Processor Technologies Group led by Prof. Steve Furber. My research is mainly focused on developing EDAs for synthesising integrated synchronous-asynchronous structures at SoC level. The eTeak synthesis platform is developed during the course of my PhD research and consists the following contributions namely: 1)Automatic Clock 2) RTL re-synthesis, and 3) D-elastisation. eTeak enables the designer to explore GALS-like architectures from a higher abstration level. I… Show more I'm a member of the Advanced Processor Technologies Group led by Prof. Steve Furber. My research is mainly focused on developing EDAs for synthesising integrated synchronous-asynchronous structures at SoC level. The eTeak synthesis platform is developed during the course of my PhD research and consists the following contributions namely: 1)Automatic Clock 2) RTL re-synthesis, and 3) D-elastisation. eTeak enables the designer to explore GALS-like architectures from a higher abstration level. I was a collaborator on GAELS project (supported by EPSRC under research grant EP/I038306/1).



University of Southern California

• United States
• Medical Practices
• 1 - 100 Employee

• Research Scholar

  • Sep 2016 - Nov 2016

  Greater Los Angeles Area I was hosted by Prof. Peter Beerel at CAD/VLSI Group of USC. Early days of implementing Deep Neural Network models on multiple FPGA systems. This project was sponsored by my EPSRC fellowship in 2016-2017.



Newcastle University

• United Kingdom
• Higher Education
• 700 & Above Employee

• Research Consultant

  • Apr 2015 - Sep 2015

  Newcastle upon Tyne, United Kingdom Worked under µSystems Design Group at Newcastle University under Prof. Alex Yakovlev as part of the GAELS project since April 2015. In our collaboration we aimed at answering: What degree of elasticity is enough? My PhD research framework, called eTeak, which enable the designer explore elasticity at different levels of granularity towards Globally Asynchronous/Elastic Locally Synchronous (GALS-SoC) design from a high-level perspective. Our recent work is based on eTeak where we have… Show more Worked under µSystems Design Group at Newcastle University under Prof. Alex Yakovlev as part of the GAELS project since April 2015. In our collaboration we aimed at answering: What degree of elasticity is enough? My PhD research framework, called eTeak, which enable the designer explore elasticity at different levels of granularity towards Globally Asynchronous/Elastic Locally Synchronous (GALS-SoC) design from a high-level perspective. Our recent work is based on eTeak where we have coined the "Vertical and Horizontal Elasticity" terms in a sense that exploring elasticity at Description Level (DL), Cycle Level (CL), Register-Transfer-Level (RTL) and Gate Level (GL) is considered as Vertical exploration whilst the algorithmic explorations regrading the computation models are considered as Horizontal exploration in the context of elasticity. Show less