Madhan Jaganathan

Head of Software, AI/ML on 5G at Aira Technologies
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Contact Information
us****@****om
(386) 825-5501
Location
Cupertino, California, United States, US
Skills

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Credentials

  • XCS229i - Machine Learning
    Stanford Online
    Jun, 2021
    - Nov, 2024

Experience

  • Aira Technologies
    • United States
    • Wireless Services
    • 1 - 100 Employee
    • Head of Software, AI/ML on 5G
      • 2022 - Present

      Leading the software team enabling AI for wireless 5G Leading the software team enabling AI for wireless 5G

  • RADAR
    • United States
    • Wireless Services
    • 1 - 100 Employee
    • Head / Sensor Software
      • 2021 - 2022

      Led the sensor & controller software team with focus on retail locationing Led the sensor & controller software team with focus on retail locationing

  • RUCKUS Networks
    • United States
    • Software Development
    • 700 & Above Employee
    • Director, Wireless Engineering
      • 2018 - 2021

      Leading a global org (~25 person team) responsible for the Wireless Software stack across all of Ruckus access point portfolio. Execution lead for Ruckus Wi-Fi 6 products driving cross-functional teams while the adoption ramped up to xM+ shipments and xxxM+ in revenue. Improved user experience of video/voice conferencing usage in dense Wi-Fi deployments with enhancements to the Channel occupancy and Quality of Service. Handled customer deployment issues of xxM+ access points in production and fed the learnings back to the development cycle for continuously improvement. Collaborated with silicon vendors and bridged the gap from an end user experience to the chipset specification and functionality. Worked with Product Management to steer product and technology roadmap. Show less

  • Qualcomm
    • United States
    • Telecommunications
    • 700 & Above Employee
    • Principal Manager, Firmware
      • 2011 - 2018

      Started in a systems/architecture role and grew up to Principal manager leading 2 major WI-FI generations (11ac-wav2, 11ax chipsets) as Project engineer for the firmware team. Co-designed the HW/SW partition while working with the baseband/mac/systems architects and vetted the PRD requests with product management. Represented firmware team to executive management, coordinated a 25 member team across 3-differenet GEO’s . streamlined execution to unwind choke points and balanced feature development and stability to adhere to project timelines. Key Wi-Fi features to be developed were TxBF, MU-MIMO, OFDMA and scheduler/queueing re-architecture to meet performance KPI's. Fine-tuned CPU performance to meet the packets per second specification, optimized memory partitions, migrated firmware execution from a single thread to multi-threaded system. Pushed hardware acceleration in newer generation based on firmware bottlenecks of the previous generation to reach better KPI targets Streamlined project execution specifically unblocking problems that falls in the boundary areas between functional teams. Engaged with early access partners to present architecture/re-flowed the feedback to development cycle and supported the customer through their productization. Show less

  • Atheros Communications
    • United States
    • Semiconductors
    • 100 - 200 Employee
    • Systems Lead
      • 2009 - 2011

      Owned the HW/SW interface and calibration reference code used for chipset bring-up/validation Systems responsibility of end of end chip functionality with focus on wireless performance for 11n generation of wireless chipsets including bluetooth/wifi combo chipsets. Owned the HW/SW interface and calibration reference code used for chipset bring-up/validation Systems responsibility of end of end chip functionality with focus on wireless performance for 11n generation of wireless chipsets including bluetooth/wifi combo chipsets.

  • Realtek Semiconductor Corp. Wionics Research
    • Asic and Systems Engineer
      • 2007 - 2009

      Worked on Wireless USB products in a startup role spanning matlab analysis, verilog chip design and embedded software work Worked on Wireless USB products in a startup role spanning matlab analysis, verilog chip design and embedded software work

  • Texas Instruments
    • United States
    • Semiconductor Manufacturing
    • 700 & Above Employee
    • Design Engineer
      • 2002 - 2005

      Worked on RTL chip design /Verilog code of the 11a/b/g generations of wireless chips. Re-designed of baseband modules like AGC, Receive Time domain processing, Correlator blocks for chip cost optimization and more robust design. Ran FPGA emulation to ensure bit error rate vs SNR is within spec across various RF impairments. Performed ECO's on synthesized netlist for late design changes. Analyzed ATPG tools and tweaked RTL to to ensure stuck at coverage > 95% Worked on RTL chip design /Verilog code of the 11a/b/g generations of wireless chips. Re-designed of baseband modules like AGC, Receive Time domain processing, Correlator blocks for chip cost optimization and more robust design. Ran FPGA emulation to ensure bit error rate vs SNR is within spec across various RF impairments. Performed ECO's on synthesized netlist for late design changes. Analyzed ATPG tools and tweaked RTL to to ensure stuck at coverage > 95%

Education

  • College of Engineering, Guindy
    Bachelor of Science, Electronics and Communication
  • University of California, Santa Cruz
    Masters of Science, Electrical Engineering

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